
Robert Whittenbaugh
Examiner (ID: 10240)
| Most Active Art Unit | 1201 |
| Art Unit(s) | 1201 |
| Total Applications | 889 |
| Issued Applications | 802 |
| Pending Applications | 0 |
| Abandoned Applications | 87 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 18599010
[patent_doc_number] => 20230273810
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-08-31
[patent_title] => PROGRAM EVENT RECORDING STORAGE ALTERATION PROCESSING FOR A NEURAL NETWORK ACCELERATOR INSTRUCTION
[patent_app_type] => utility
[patent_app_number] => 18/308793
[patent_app_country] => US
[patent_app_date] => 2023-04-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 26144
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -20
[patent_words_short_claim] => 100
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18308793
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/308793 | Program event recording storage alteration processing for a neural network accelerator instruction | Apr 27, 2023 | Issued |
Array
(
[id] => 18630416
[patent_doc_number] => 20230289309
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-09-14
[patent_title] => MULTICHIP PACKAGE WITH PROTOCOL-CONFIGURABLE DATA PATHS
[patent_app_type] => utility
[patent_app_number] => 18/306100
[patent_app_country] => US
[patent_app_date] => 2023-04-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5818
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18306100
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/306100 | Multichip package with protocol-configurable data paths | Apr 23, 2023 | Issued |
Array
(
[id] => 19530364
[patent_doc_number] => 20240354266
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-10-24
[patent_title] => PIN-CONSTRAINED DEVICES
[patent_app_type] => utility
[patent_app_number] => 18/305679
[patent_app_country] => US
[patent_app_date] => 2023-04-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9554
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 71
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18305679
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/305679 | Pin-constrained devices | Apr 23, 2023 | Issued |
Array
(
[id] => 19530362
[patent_doc_number] => 20240354264
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-10-24
[patent_title] => INTELLIGENT WORKSPACE CONNECTION ASSISTANCE
[patent_app_type] => utility
[patent_app_number] => 18/302035
[patent_app_country] => US
[patent_app_date] => 2023-04-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7125
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 54
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18302035
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/302035 | Intelligent workspace connection assistance | Apr 17, 2023 | Issued |
Array
(
[id] => 19581264
[patent_doc_number] => 12147377
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-11-19
[patent_title] => Distributed multi-die protocol application interface
[patent_app_type] => utility
[patent_app_number] => 18/299662
[patent_app_country] => US
[patent_app_date] => 2023-04-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 6
[patent_no_of_words] => 4851
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 99
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18299662
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/299662 | Distributed multi-die protocol application interface | Apr 11, 2023 | Issued |
Array
(
[id] => 19228740
[patent_doc_number] => 12008378
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-06-11
[patent_title] => Mechanism for reducing coherence directory controller overhead for near-memory compute elements
[patent_app_type] => utility
[patent_app_number] => 18/132879
[patent_app_country] => US
[patent_app_date] => 2023-04-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 4413
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 73
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18132879
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/132879 | Mechanism for reducing coherence directory controller overhead for near-memory compute elements | Apr 9, 2023 | Issued |
Array
(
[id] => 18659844
[patent_doc_number] => 20230305851
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-09-28
[patent_title] => MODULAR PIPELINES FOR ACCESSING DIGITAL DATA
[patent_app_type] => utility
[patent_app_number] => 18/126603
[patent_app_country] => US
[patent_app_date] => 2023-03-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 13696
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -28
[patent_words_short_claim] => 92
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18126603
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/126603 | Modular pipelines for accessing digital data | Mar 26, 2023 | Issued |
Array
(
[id] => 19732879
[patent_doc_number] => 12210877
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-01-28
[patent_title] => Offloading computation based on extended instruction set architecture
[patent_app_type] => utility
[patent_app_number] => 18/118367
[patent_app_country] => US
[patent_app_date] => 2023-03-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 20
[patent_figures_cnt] => 20
[patent_no_of_words] => 8771
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 136
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18118367
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/118367 | Offloading computation based on extended instruction set architecture | Mar 6, 2023 | Issued |
Array
(
[id] => 18839312
[patent_doc_number] => 11847386
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2023-12-19
[patent_title] => Artificial intelligence based on cellular automata
[patent_app_type] => utility
[patent_app_number] => 18/113280
[patent_app_country] => US
[patent_app_date] => 2023-02-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 59
[patent_figures_cnt] => 59
[patent_no_of_words] => 66506
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 102
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18113280
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/113280 | Artificial intelligence based on cellular automata | Feb 22, 2023 | Issued |
Array
(
[id] => 18532963
[patent_doc_number] => 20230238038
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-07-27
[patent_title] => APPARATUSES AND METHODS FOR STORING AND WRITING MULTIPLE PARAMETER CODES FOR MEMORY OPERATING PARAMETERS
[patent_app_type] => utility
[patent_app_number] => 18/157945
[patent_app_country] => US
[patent_app_date] => 2023-01-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6961
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 97
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18157945
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/157945 | Apparatuses and methods for storing and writing multiple parameter codes for memory operating parameters | Jan 22, 2023 | Issued |
Array
(
[id] => 18638098
[patent_doc_number] => 11762700
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-09-19
[patent_title] => High-energy-efficiency binary neural network accelerator applicable to artificial intelligence internet of things
[patent_app_type] => utility
[patent_app_number] => 18/098746
[patent_app_country] => US
[patent_app_date] => 2023-01-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 22
[patent_no_of_words] => 5431
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 287
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18098746
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/098746 | High-energy-efficiency binary neural network accelerator applicable to artificial intelligence internet of things | Jan 18, 2023 | Issued |
Array
(
[id] => 18407955
[patent_doc_number] => 20230169308
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-06-01
[patent_title] => Neural Network Processor for Handling Differing Datatypes
[patent_app_type] => utility
[patent_app_number] => 18/095960
[patent_app_country] => US
[patent_app_date] => 2023-01-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9947
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 109
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18095960
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/095960 | Neural network processor for handling differing datatypes | Jan 10, 2023 | Issued |
Array
(
[id] => 18651692
[patent_doc_number] => 20230297528
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-09-21
[patent_title] => SEMICONDUCTOR DEVICE
[patent_app_type] => utility
[patent_app_number] => 18/152582
[patent_app_country] => US
[patent_app_date] => 2023-01-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8277
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -9
[patent_words_short_claim] => 297
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18152582
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/152582 | Semiconductor device | Jan 9, 2023 | Issued |
Array
(
[id] => 19552281
[patent_doc_number] => 12135990
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-11-05
[patent_title] => Modeling and compiling tensor processing applications for a computing platform using multi-layer adaptive data flow graphs
[patent_app_type] => utility
[patent_app_number] => 18/091907
[patent_app_country] => US
[patent_app_date] => 2022-12-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 28
[patent_figures_cnt] => 29
[patent_no_of_words] => 11951
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 139
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18091907
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/091907 | Modeling and compiling tensor processing applications for a computing platform using multi-layer adaptive data flow graphs | Dec 29, 2022 | Issued |
Array
(
[id] => 19283972
[patent_doc_number] => 20240220448
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-07-04
[patent_title] => SCALABLE AND CONFIGURABLE CLUSTERED SYSTOLIC ARRAY
[patent_app_type] => utility
[patent_app_number] => 18/148998
[patent_app_country] => US
[patent_app_date] => 2022-12-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 46676
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 111
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18148998
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/148998 | SCALABLE AND CONFIGURABLE CLUSTERED SYSTOLIC ARRAY | Dec 29, 2022 | Pending |
Array
(
[id] => 19283968
[patent_doc_number] => 20240220444
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-07-04
[patent_title] => SCALABLE ACCELERATION OF REENTRANT COMPUTE OPERATIONS
[patent_app_type] => utility
[patent_app_number] => 18/089780
[patent_app_country] => US
[patent_app_date] => 2022-12-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8833
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 130
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18089780
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/089780 | Scalable acceleration of reentrant compute operations | Dec 27, 2022 | Issued |
Array
(
[id] => 19267558
[patent_doc_number] => 20240211261
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-06-27
[patent_title] => ACCELERATING FOUR-WAY PARALLEL KECCAK EXECUTION ON 256-BIT VECTOR PROCESSOR
[patent_app_type] => utility
[patent_app_number] => 18/145776
[patent_app_country] => US
[patent_app_date] => 2022-12-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 12672
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 174
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18145776
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/145776 | Accelerating four-way parallel KECCAK execution on 256-bit vector processor | Dec 21, 2022 | Issued |
Array
(
[id] => 18838965
[patent_doc_number] => 11847036
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-12-19
[patent_title] => Fault isolation and recovery of CPU cores for failed secondary asymmetric multiprocessing instance
[patent_app_type] => utility
[patent_app_number] => 18/067897
[patent_app_country] => US
[patent_app_date] => 2022-12-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 8655
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 60
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18067897
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/067897 | Fault isolation and recovery of CPU cores for failed secondary asymmetric multiprocessing instance | Dec 18, 2022 | Issued |
Array
(
[id] => 19251010
[patent_doc_number] => 20240202000
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-06-20
[patent_title] => DEVICE, METHOD AND SYSTEM TO CAPTURE OR RESTORE MICROARCHITECTURAL STATE OF A PROCESSOR CORE
[patent_app_type] => utility
[patent_app_number] => 18/084425
[patent_app_country] => US
[patent_app_date] => 2022-12-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 17579
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 68
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18084425
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/084425 | DEVICE, METHOD AND SYSTEM TO CAPTURE OR RESTORE MICROARCHITECTURAL STATE OF A PROCESSOR CORE | Dec 18, 2022 | Pending |
Array
(
[id] => 18839390
[patent_doc_number] => 11847464
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-12-19
[patent_title] => Variable pipeline length in a barrel-multithreaded processor
[patent_app_type] => utility
[patent_app_number] => 18/079164
[patent_app_country] => US
[patent_app_date] => 2022-12-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 7
[patent_no_of_words] => 13475
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 85
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18079164
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/079164 | Variable pipeline length in a barrel-multithreaded processor | Dec 11, 2022 | Issued |