Search

Roberta D. Prendergast

Examiner (ID: 3669, Phone: (571)272-7647 , Office: P/2611 )

Most Active Art Unit
2628
Art Unit(s)
2614, 2611, 2679, 2628, 2671
Total Applications
255
Issued Applications
133
Pending Applications
10
Abandoned Applications
112

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5414932 [patent_doc_number] => 20090040819 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-02-12 [patent_title] => 'NONVOLATILE MEMORY DEVICE USING RESISTIVE ELEMENTS AND AN ASSOCIATED DRIVING METHOD' [patent_app_type] => utility [patent_app_number] => 12/186649 [patent_app_country] => US [patent_app_date] => 2008-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 4309 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0040/20090040819.pdf [firstpage_image] =>[orig_patent_app_number] => 12186649 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/186649
Nonvolatile memory device using resistive elements and an associated driving method Aug 5, 2008 Issued
Array ( [id] => 4435978 [patent_doc_number] => 07969809 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-06-28 [patent_title] => 'Power consumption-oriented management of a storage system' [patent_app_type] => utility [patent_app_number] => 12/186409 [patent_app_country] => US [patent_app_date] => 2008-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 7796 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/969/07969809.pdf [firstpage_image] =>[orig_patent_app_number] => 12186409 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/186409
Power consumption-oriented management of a storage system Aug 4, 2008 Issued
Array ( [id] => 5445308 [patent_doc_number] => 20090046534 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-02-19 [patent_title] => 'Method of Operating a Memory Apparatus, Memory Device and Memory Apparatus' [patent_app_type] => utility [patent_app_number] => 12/186195 [patent_app_country] => US [patent_app_date] => 2008-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 7662 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0046/20090046534.pdf [firstpage_image] =>[orig_patent_app_number] => 12186195 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/186195
Method of operating a memory apparatus, memory device and memory apparatus Aug 4, 2008 Issued
Array ( [id] => 4467971 [patent_doc_number] => 07936628 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-05-03 [patent_title] => 'Semiconductor memory and method for operating a semiconductor memory' [patent_app_type] => utility [patent_app_number] => 12/186085 [patent_app_country] => US [patent_app_date] => 2008-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 4991 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/936/07936628.pdf [firstpage_image] =>[orig_patent_app_number] => 12186085 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/186085
Semiconductor memory and method for operating a semiconductor memory Aug 4, 2008 Issued
Array ( [id] => 6249758 [patent_doc_number] => 20100027367 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-02-04 [patent_title] => 'ROW MASK ADDRESSING' [patent_app_type] => utility [patent_app_number] => 12/185709 [patent_app_country] => US [patent_app_date] => 2008-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7713 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0027/20100027367.pdf [firstpage_image] =>[orig_patent_app_number] => 12185709 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/185709
Row mask addressing Aug 3, 2008 Issued
Array ( [id] => 5414917 [patent_doc_number] => 20090040804 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-02-12 [patent_title] => 'FUSE CIRCUIT' [patent_app_type] => utility [patent_app_number] => 12/185183 [patent_app_country] => US [patent_app_date] => 2008-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 9806 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0040/20090040804.pdf [firstpage_image] =>[orig_patent_app_number] => 12185183 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/185183
Fuse circuit Aug 3, 2008 Issued
Array ( [id] => 45015 [patent_doc_number] => 07782686 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-08-24 [patent_title] => 'Method and apparatus for timing adjustment' [patent_app_type] => utility [patent_app_number] => 12/184797 [patent_app_country] => US [patent_app_date] => 2008-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 9585 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/782/07782686.pdf [firstpage_image] =>[orig_patent_app_number] => 12184797 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/184797
Method and apparatus for timing adjustment Jul 31, 2008 Issued
Array ( [id] => 198891 [patent_doc_number] => 07639537 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-12-29 [patent_title] => 'Method for writing data in a non volatile memory unit' [patent_app_type] => utility [patent_app_number] => 12/184643 [patent_app_country] => US [patent_app_date] => 2008-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 3266 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/639/07639537.pdf [firstpage_image] =>[orig_patent_app_number] => 12184643 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/184643
Method for writing data in a non volatile memory unit Jul 31, 2008 Issued
Array ( [id] => 4565120 [patent_doc_number] => 07821845 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-10-26 [patent_title] => 'Write driver circuit of an unmuxed bit line scheme' [patent_app_type] => utility [patent_app_number] => 12/184321 [patent_app_country] => US [patent_app_date] => 2008-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2857 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/821/07821845.pdf [firstpage_image] =>[orig_patent_app_number] => 12184321 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/184321
Write driver circuit of an unmuxed bit line scheme Jul 31, 2008 Issued
Array ( [id] => 221998 [patent_doc_number] => 07609545 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-10-27 [patent_title] => 'Semiconductor device' [patent_app_type] => utility [patent_app_number] => 12/180523 [patent_app_country] => US [patent_app_date] => 2008-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 22 [patent_no_of_words] => 9018 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/609/07609545.pdf [firstpage_image] =>[orig_patent_app_number] => 12180523 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/180523
Semiconductor device Jul 25, 2008 Issued
Array ( [id] => 5440335 [patent_doc_number] => 20090091974 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-04-09 [patent_title] => 'Methods of programming non-volatile memory cells' [patent_app_type] => utility [patent_app_number] => 12/219663 [patent_app_country] => US [patent_app_date] => 2008-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6660 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0091/20090091974.pdf [firstpage_image] =>[orig_patent_app_number] => 12219663 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/219663
Methods of programming non-volatile memory cells Jul 24, 2008 Issued
Array ( [id] => 24666 [patent_doc_number] => 07800964 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-09-21 [patent_title] => 'Wafer burn-in test circuit' [patent_app_type] => utility [patent_app_number] => 12/179491 [patent_app_country] => US [patent_app_date] => 2008-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 4968 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/800/07800964.pdf [firstpage_image] =>[orig_patent_app_number] => 12179491 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/179491
Wafer burn-in test circuit Jul 23, 2008 Issued
Array ( [id] => 5519958 [patent_doc_number] => 20090027939 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-01-29 [patent_title] => 'MULTI-CHIP PACKAGE REDUCING POWER-UP PEAK CURRENT' [patent_app_type] => utility [patent_app_number] => 12/177323 [patent_app_country] => US [patent_app_date] => 2008-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 5160 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0027/20090027939.pdf [firstpage_image] =>[orig_patent_app_number] => 12177323 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/177323
Multi-chip package reducing power-up peak current Jul 21, 2008 Issued
Array ( [id] => 5269969 [patent_doc_number] => 20090073745 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-03-19 [patent_title] => 'SEMICONDUCTOR INTEGRATED CIRCUIT' [patent_app_type] => utility [patent_app_number] => 12/176703 [patent_app_country] => US [patent_app_date] => 2008-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5820 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0073/20090073745.pdf [firstpage_image] =>[orig_patent_app_number] => 12176703 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/176703
Semiconductor integrated circuit Jul 20, 2008 Issued
Array ( [id] => 5451182 [patent_doc_number] => 20090067218 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-03-12 [patent_title] => 'Sense amplifier circuitry for integrated circuit having memory cell array, and method of operating same' [patent_app_type] => utility [patent_app_number] => 12/218895 [patent_app_country] => US [patent_app_date] => 2008-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 29 [patent_no_of_words] => 13894 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0067/20090067218.pdf [firstpage_image] =>[orig_patent_app_number] => 12218895 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/218895
Sense amplifier circuitry for integrated circuit having memory cell array, and method of operating same Jul 17, 2008 Issued
Array ( [id] => 4584699 [patent_doc_number] => 07826291 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-11-02 [patent_title] => 'Precharge and evaluation phase circuits for sense amplifiers' [patent_app_type] => utility [patent_app_number] => 12/174307 [patent_app_country] => US [patent_app_date] => 2008-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 15 [patent_no_of_words] => 6744 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/826/07826291.pdf [firstpage_image] =>[orig_patent_app_number] => 12174307 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/174307
Precharge and evaluation phase circuits for sense amplifiers Jul 15, 2008 Issued
Array ( [id] => 5390351 [patent_doc_number] => 20090207664 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-08-20 [patent_title] => 'Flash Memory Device for Variably Controlling Program Voltage and Method of Programming the Same' [patent_app_type] => utility [patent_app_number] => 12/171701 [patent_app_country] => US [patent_app_date] => 2008-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4668 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0207/20090207664.pdf [firstpage_image] =>[orig_patent_app_number] => 12171701 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/171701
Flash memory device for variably controlling program voltage and method of programming the same Jul 10, 2008 Issued
Array ( [id] => 5308845 [patent_doc_number] => 20090016126 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-01-15 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 12/170561 [patent_app_country] => US [patent_app_date] => 2008-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 8430 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0016/20090016126.pdf [firstpage_image] =>[orig_patent_app_number] => 12170561 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/170561
Semiconductor memory device Jul 9, 2008 Issued
Array ( [id] => 105291 [patent_doc_number] => 07724591 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-05-25 [patent_title] => 'Semiconductor memory device and local input/output division method' [patent_app_type] => utility [patent_app_number] => 12/169947 [patent_app_country] => US [patent_app_date] => 2008-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 4171 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/724/07724591.pdf [firstpage_image] =>[orig_patent_app_number] => 12169947 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/169947
Semiconductor memory device and local input/output division method Jul 8, 2008 Issued
Array ( [id] => 5308822 [patent_doc_number] => 20090016103 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-01-15 [patent_title] => 'MSB-BASED ERROR CORRECTION FOR FLASH MEMORY SYSTEM' [patent_app_type] => utility [patent_app_number] => 12/169109 [patent_app_country] => US [patent_app_date] => 2008-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 10951 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0016/20090016103.pdf [firstpage_image] =>[orig_patent_app_number] => 12169109 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/169109
MSB-based error correction for flash memory system Jul 7, 2008 Issued
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