
Roberto Velez
Supervisory Patent Examiner (ID: 6169, Phone: (571)272-8597 , Office: P/2662 )
| Most Active Art Unit | 2829 |
| Art Unit(s) | 2829, 2662, 2858, 3600 |
| Total Applications | 504 |
| Issued Applications | 309 |
| Pending Applications | 75 |
| Abandoned Applications | 135 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 4724527
[patent_doc_number] => 20080204068
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-08-28
[patent_title] => 'METHOD FOR ESTIMATING DEFECTS IN AN NPN TRANSISTOR ARRAY'
[patent_app_type] => utility
[patent_app_number] => 11/680283
[patent_app_country] => US
[patent_app_date] => 2007-02-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 2229
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0204/20080204068.pdf
[firstpage_image] =>[orig_patent_app_number] => 11680283
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/680283 | METHOD FOR ESTIMATING DEFECTS IN AN NPN TRANSISTOR ARRAY | Feb 27, 2007 | Abandoned |
Array
(
[id] => 203673
[patent_doc_number] => 07633308
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2009-12-15
[patent_title] => 'Combined pulse and DC test system'
[patent_app_type] => utility
[patent_app_number] => 11/704479
[patent_app_country] => US
[patent_app_date] => 2007-02-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 1348
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 110
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/633/07633308.pdf
[firstpage_image] =>[orig_patent_app_number] => 11704479
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/704479 | Combined pulse and DC test system | Feb 8, 2007 | Issued |
Array
(
[id] => 5003018
[patent_doc_number] => 20070200585
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-08-30
[patent_title] => 'Semiconductor wafer, semiconductor chip, semiconductor device, and wafer testing method'
[patent_app_type] => utility
[patent_app_number] => 11/702180
[patent_app_country] => US
[patent_app_date] => 2007-02-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 15
[patent_no_of_words] => 10454
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 4
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[patent_maintenance] => 1
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0200/20070200585.pdf
[firstpage_image] =>[orig_patent_app_number] => 11702180
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/702180 | Semiconductor wafer, semiconductor chip, semiconductor device, and wafer testing method | Feb 4, 2007 | Abandoned |
Array
(
[id] => 330971
[patent_doc_number] => 07511470
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-03-31
[patent_title] => 'Electronic tamper detection circuit for an electricity meter'
[patent_app_type] => utility
[patent_app_number] => 11/668180
[patent_app_country] => US
[patent_app_date] => 2007-01-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 8
[patent_no_of_words] => 5080
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 206
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/511/07511470.pdf
[firstpage_image] =>[orig_patent_app_number] => 11668180
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/668180 | Electronic tamper detection circuit for an electricity meter | Jan 28, 2007 | Issued |
Array
(
[id] => 4774794
[patent_doc_number] => 20080282792
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-11-20
[patent_title] => 'Device and Method For Measuring and Monitoring the Level of Liquid Metal in a Crystalliser'
[patent_app_type] => utility
[patent_app_number] => 12/162259
[patent_app_country] => US
[patent_app_date] => 2007-01-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 3598
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0282/20080282792.pdf
[firstpage_image] =>[orig_patent_app_number] => 12162259
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/162259 | Device and method for measuring and monitoring the level of liquid metal in a crystalliser | Jan 25, 2007 | Issued |
Array
(
[id] => 5093412
[patent_doc_number] => 20070115021
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-05-24
[patent_title] => 'TESTING METHOD FOR ARRAY SUBSTRATE'
[patent_app_type] => utility
[patent_app_number] => 11/626530
[patent_app_country] => US
[patent_app_date] => 2007-01-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 7363
[patent_no_of_claims] => 4
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[patent_maintenance] => 1
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0115/20070115021.pdf
[firstpage_image] =>[orig_patent_app_number] => 11626530
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/626530 | Testing method for array substrate | Jan 23, 2007 | Issued |
Array
(
[id] => 5340982
[patent_doc_number] => 20090179632
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-07-16
[patent_title] => 'Magnetic Resolver'
[patent_app_type] => utility
[patent_app_number] => 12/087101
[patent_app_country] => US
[patent_app_date] => 2006-12-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 8991
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0179/20090179632.pdf
[firstpage_image] =>[orig_patent_app_number] => 12087101
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/087101 | Magnetic resolver | Dec 21, 2006 | Issued |
Array
(
[id] => 810745
[patent_doc_number] => 07417450
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-08-26
[patent_title] => 'Testing combinational logic die with bidirectional TDI-TMS/TDO chanel circuit'
[patent_app_type] => utility
[patent_app_number] => 11/565979
[patent_app_country] => US
[patent_app_date] => 2006-12-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 23
[patent_no_of_words] => 4400
[patent_no_of_claims] => 1
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 236
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/417/07417450.pdf
[firstpage_image] =>[orig_patent_app_number] => 11565979
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/565979 | Testing combinational logic die with bidirectional TDI-TMS/TDO chanel circuit | Nov 30, 2006 | Issued |
Array
(
[id] => 4963432
[patent_doc_number] => 20080106252
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-05-08
[patent_title] => 'INTEGRATED CURRENT SENSING TRANSFORMER AND CURRENT SENSING CIRCUIT USING SUCH TRANSFORMER'
[patent_app_type] => utility
[patent_app_number] => 11/564978
[patent_app_country] => US
[patent_app_date] => 2006-11-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
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[patent_no_of_claims] => 20
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0106/20080106252.pdf
[firstpage_image] =>[orig_patent_app_number] => 11564978
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/564978 | Integrated current sensing transformer and current sensing circuit using such transformer | Nov 29, 2006 | Issued |
Array
(
[id] => 5039235
[patent_doc_number] => 20070091517
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-04-26
[patent_title] => 'SYSTEM AND METHOD FOR REGENERATIVE BURN-IN'
[patent_app_type] => utility
[patent_app_number] => 11/557912
[patent_app_country] => US
[patent_app_date] => 2006-11-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 15
[patent_no_of_words] => 3944
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 2
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0091/20070091517.pdf
[firstpage_image] =>[orig_patent_app_number] => 11557912
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/557912 | SYSTEM AND METHOD FOR REGENERATIVE BURN-IN | Nov 7, 2006 | Abandoned |
Array
(
[id] => 5181066
[patent_doc_number] => 20070052408
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-03-08
[patent_title] => 'Current measuring device'
[patent_app_type] => utility
[patent_app_number] => 11/593564
[patent_app_country] => US
[patent_app_date] => 2006-11-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
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[pdf_file] => publications/A1/0052/20070052408.pdf
[firstpage_image] =>[orig_patent_app_number] => 11593564
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/593564 | Current measuring device | Nov 6, 2006 | Issued |
Array
(
[id] => 5197116
[patent_doc_number] => 20070296434
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-12-27
[patent_title] => 'Temperature control method and apparatus and test method and apparatus of semiconductor devices'
[patent_app_type] => utility
[patent_app_number] => 11/585284
[patent_app_country] => US
[patent_app_date] => 2006-10-24
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[pdf_file] => publications/A1/0296/20070296434.pdf
[firstpage_image] =>[orig_patent_app_number] => 11585284
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/585284 | Temperature control method and apparatus and test method and apparatus of semiconductor devices | Oct 23, 2006 | Abandoned |
Array
(
[id] => 7541045
[patent_doc_number] => 08058891
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-11-15
[patent_title] => 'Delay lock loop circuit, timing generator, semiconductor test device, semiconductor integrated circuit, and delay amount calibration method'
[patent_app_type] => utility
[patent_app_number] => 12/083577
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[pdf_file] => patents/08/058/08058891.pdf
[firstpage_image] =>[orig_patent_app_number] => 12083577
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/083577 | Delay lock loop circuit, timing generator, semiconductor test device, semiconductor integrated circuit, and delay amount calibration method | Oct 17, 2006 | Issued |
Array
(
[id] => 881409
[patent_doc_number] => 07355377
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2008-04-08
[patent_title] => 'Telescoping electrical tester'
[patent_app_type] => utility
[patent_app_number] => 11/581982
[patent_app_country] => US
[patent_app_date] => 2006-10-17
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/07/355/07355377.pdf
[firstpage_image] =>[orig_patent_app_number] => 11581982
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/581982 | Telescoping electrical tester | Oct 16, 2006 | Issued |
Array
(
[id] => 5234284
[patent_doc_number] => 20070126439
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-06-07
[patent_title] => 'METHODS AND APPARATUS FOR CREATING A HIGH SPEED CONNECTION BETWEEN A DEVICE UNDER TEST AND AUTOMATIC TEST EQUIPMENT'
[patent_app_type] => utility
[patent_app_number] => 11/548382
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[patent_effective_date] => 0000-00-00
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[pdf_file] => publications/A1/0126/20070126439.pdf
[firstpage_image] =>[orig_patent_app_number] => 11548382
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/548382 | METHODS AND APPARATUS FOR CREATING A HIGH SPEED CONNECTION BETWEEN A DEVICE UNDER TEST AND AUTOMATIC TEST EQUIPMENT | Oct 10, 2006 | Abandoned |
Array
(
[id] => 8665199
[patent_doc_number] => 08378662
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2013-02-19
[patent_title] => 'Current sensor'
[patent_app_type] => utility
[patent_app_number] => 12/162127
[patent_app_country] => US
[patent_app_date] => 2006-10-07
[patent_effective_date] => 0000-00-00
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[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12162127
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/162127 | Current sensor | Oct 6, 2006 | Issued |
Array
(
[id] => 5037269
[patent_doc_number] => 20070089551
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-04-26
[patent_title] => 'Cantilever probe structure for a probe card assembly'
[patent_app_type] => utility
[patent_app_number] => 11/529784
[patent_app_country] => US
[patent_app_date] => 2006-09-29
[patent_effective_date] => 0000-00-00
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[pdf_file] => publications/A1/0089/20070089551.pdf
[firstpage_image] =>[orig_patent_app_number] => 11529784
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/529784 | Cantilever probe structure for a probe card assembly | Sep 28, 2006 | Abandoned |
Array
(
[id] => 203640
[patent_doc_number] => 07633288
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-12-15
[patent_title] => 'Method of testing semiconductor devices and handler used for testing semiconductor devices'
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[pdf_file] => patents/07/633/07633288.pdf
[firstpage_image] =>[orig_patent_app_number] => 11527378
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/527378 | Method of testing semiconductor devices and handler used for testing semiconductor devices | Sep 26, 2006 | Issued |
Array
(
[id] => 5038543
[patent_doc_number] => 20070090825
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-04-26
[patent_title] => 'Current sensor'
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[pdf_file] => publications/A1/0090/20070090825.pdf
[firstpage_image] =>[orig_patent_app_number] => 11526683
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/526683 | Current sensor | Sep 25, 2006 | Issued |
Array
(
[id] => 4907584
[patent_doc_number] => 20080018350
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-01-24
[patent_title] => 'Test probe for integrated circuits with ultra-fine pitch terminals'
[patent_app_type] => utility
[patent_app_number] => 11/525581
[patent_app_country] => US
[patent_app_date] => 2006-09-22
[patent_effective_date] => 0000-00-00
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0018/20080018350.pdf
[firstpage_image] =>[orig_patent_app_number] => 11525581
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/525581 | Test probe for integrated circuits with ultra-fine pitch terminals | Sep 21, 2006 | Abandoned |