Search

Rocio Del Mar Perez-velez

Examiner (ID: 4591, Phone: (571)270-5935 , Office: P/2132 )

Most Active Art Unit
2132
Art Unit(s)
2182, 2100, 2187, 2117, 2133, 2132
Total Applications
254
Issued Applications
200
Pending Applications
5
Abandoned Applications
50

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17933302 [patent_doc_number] => 20220328428 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-13 [patent_title] => MOISTURE BARRIER FOR BOND PADS AND INTEGRATED CIRCUIT HAVING THE SAME [patent_app_type] => utility [patent_app_number] => 17/809257 [patent_app_country] => US [patent_app_date] => 2022-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10086 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17809257 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/809257
Moisture barrier for bond pads and integrated circuit having the same Jun 26, 2022 Issued
Array ( [id] => 20148274 [patent_doc_number] => 12382634 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-08-05 [patent_title] => Semiconductor memory device that includes a plurality of first pillars, second pillars, and third pillars [patent_app_type] => utility [patent_app_number] => 17/840686 [patent_app_country] => US [patent_app_date] => 2022-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 60 [patent_no_of_words] => 15151 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 230 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17840686 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/840686
Semiconductor memory device that includes a plurality of first pillars, second pillars, and third pillars Jun 14, 2022 Issued
Array ( [id] => 19873719 [patent_doc_number] => 12266590 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-04-01 [patent_title] => Dual side direct cooling semiconductor package [patent_app_type] => utility [patent_app_number] => 17/806961 [patent_app_country] => US [patent_app_date] => 2022-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 3836 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17806961 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/806961
Dual side direct cooling semiconductor package Jun 14, 2022 Issued
Array ( [id] => 18112939 [patent_doc_number] => 20230005819 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-01-05 [patent_title] => STACKABLE FULLY MOLDED SEMICONDUCTOR STRUCTURE WITH THROUGH SILICON VIA (TSV) VERTICAL INTERCONNECTS [patent_app_type] => utility [patent_app_number] => 17/841627 [patent_app_country] => US [patent_app_date] => 2022-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11742 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17841627 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/841627
Stackable fully molded semiconductor structure with through silicon via (TSV) vertical interconnects Jun 14, 2022 Issued
Array ( [id] => 20148274 [patent_doc_number] => 12382634 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-08-05 [patent_title] => Semiconductor memory device that includes a plurality of first pillars, second pillars, and third pillars [patent_app_type] => utility [patent_app_number] => 17/840686 [patent_app_country] => US [patent_app_date] => 2022-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 60 [patent_no_of_words] => 15151 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 230 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17840686 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/840686
Semiconductor memory device that includes a plurality of first pillars, second pillars, and third pillars Jun 14, 2022 Issued
Array ( [id] => 19223691 [patent_doc_number] => 20240188395 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-06 [patent_title] => DISPLAY PANEL AND DISPLAY TERMINAL [patent_app_type] => utility [patent_app_number] => 17/787516 [patent_app_country] => US [patent_app_date] => 2022-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6909 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17787516 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/787516
Display panel and display terminal Jun 7, 2022 Issued
Array ( [id] => 19223691 [patent_doc_number] => 20240188395 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-06 [patent_title] => DISPLAY PANEL AND DISPLAY TERMINAL [patent_app_type] => utility [patent_app_number] => 17/787516 [patent_app_country] => US [patent_app_date] => 2022-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6909 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17787516 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/787516
Display panel and display terminal Jun 7, 2022 Issued
Array ( [id] => 19223691 [patent_doc_number] => 20240188395 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-06 [patent_title] => DISPLAY PANEL AND DISPLAY TERMINAL [patent_app_type] => utility [patent_app_number] => 17/787516 [patent_app_country] => US [patent_app_date] => 2022-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6909 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17787516 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/787516
Display panel and display terminal Jun 7, 2022 Issued
Array ( [id] => 18797009 [patent_doc_number] => 11830844 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-11-28 [patent_title] => Semiconductor structure [patent_app_type] => utility [patent_app_number] => 17/834923 [patent_app_country] => US [patent_app_date] => 2022-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 42 [patent_no_of_words] => 17008 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17834923 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/834923
Semiconductor structure Jun 6, 2022 Issued
Array ( [id] => 18983588 [patent_doc_number] => 11908777 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-02-20 [patent_title] => Semiconductor package with plurality of leads and sealing resin [patent_app_type] => utility [patent_app_number] => 17/826975 [patent_app_country] => US [patent_app_date] => 2022-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 29 [patent_no_of_words] => 11718 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 242 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17826975 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/826975
Semiconductor package with plurality of leads and sealing resin May 26, 2022 Issued
Array ( [id] => 18983588 [patent_doc_number] => 11908777 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-02-20 [patent_title] => Semiconductor package with plurality of leads and sealing resin [patent_app_type] => utility [patent_app_number] => 17/826975 [patent_app_country] => US [patent_app_date] => 2022-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 29 [patent_no_of_words] => 11718 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 242 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17826975 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/826975
Semiconductor package with plurality of leads and sealing resin May 26, 2022 Issued
Array ( [id] => 18983588 [patent_doc_number] => 11908777 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-02-20 [patent_title] => Semiconductor package with plurality of leads and sealing resin [patent_app_type] => utility [patent_app_number] => 17/826975 [patent_app_country] => US [patent_app_date] => 2022-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 29 [patent_no_of_words] => 11718 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 242 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17826975 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/826975
Semiconductor package with plurality of leads and sealing resin May 26, 2022 Issued
Array ( [id] => 18983588 [patent_doc_number] => 11908777 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-02-20 [patent_title] => Semiconductor package with plurality of leads and sealing resin [patent_app_type] => utility [patent_app_number] => 17/826975 [patent_app_country] => US [patent_app_date] => 2022-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 29 [patent_no_of_words] => 11718 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 242 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17826975 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/826975
Semiconductor package with plurality of leads and sealing resin May 26, 2022 Issued
Array ( [id] => 18250764 [patent_doc_number] => 20230077803 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-16 [patent_title] => SEMICONDUCTOR DEVICES [patent_app_type] => utility [patent_app_number] => 17/751740 [patent_app_country] => US [patent_app_date] => 2022-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5908 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17751740 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/751740
Semiconductor devices including a through-hole electrode May 23, 2022 Issued
Array ( [id] => 18645663 [patent_doc_number] => 11769742 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-09-26 [patent_title] => Semiconductor chip and semiconductor package including the same [patent_app_type] => utility [patent_app_number] => 17/747190 [patent_app_country] => US [patent_app_date] => 2022-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 22 [patent_no_of_words] => 14816 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17747190 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/747190
Semiconductor chip and semiconductor package including the same May 17, 2022 Issued
Array ( [id] => 17840754 [patent_doc_number] => 20220278060 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-01 [patent_title] => MOLDED SEMICONDUCTOR PACKAGE WITH HIGH VOLTAGE ISOLATION [patent_app_type] => utility [patent_app_number] => 17/746306 [patent_app_country] => US [patent_app_date] => 2022-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5727 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17746306 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/746306
Molded semiconductor package with high voltage isolation May 16, 2022 Issued
Array ( [id] => 17949227 [patent_doc_number] => 20220336246 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-20 [patent_title] => METHOD FOR SUBSTRATE REGISTRATION AND ANCHORING IN INKJET PRINTING [patent_app_type] => utility [patent_app_number] => 17/735018 [patent_app_country] => US [patent_app_date] => 2022-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5043 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17735018 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/735018
Method for substrate registration and anchoring in inkjet printing May 1, 2022 Issued
Array ( [id] => 18721546 [patent_doc_number] => 11798903 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-24 [patent_title] => Methods of forming microvias with reduced diameter [patent_app_type] => utility [patent_app_number] => 17/725003 [patent_app_country] => US [patent_app_date] => 2022-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 5316 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17725003 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/725003
Methods of forming microvias with reduced diameter Apr 19, 2022 Issued
Array ( [id] => 18735670 [patent_doc_number] => 11804411 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-31 [patent_title] => Secure inspection and marking of semiconductor wafers for trusted manufacturing thereof [patent_app_type] => utility [patent_app_number] => 17/718390 [patent_app_country] => US [patent_app_date] => 2022-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 8933 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17718390 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/718390
Secure inspection and marking of semiconductor wafers for trusted manufacturing thereof Apr 11, 2022 Issued
Array ( [id] => 18623852 [patent_doc_number] => 11756908 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-09-12 [patent_title] => Package substrate including a redistribution pad extending from a redistribution layer and including segmenting grooves along a redial direction thereof and semiconductor package including the same [patent_app_type] => utility [patent_app_number] => 17/718639 [patent_app_country] => US [patent_app_date] => 2022-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 16 [patent_no_of_words] => 6666 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17718639 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/718639
Package substrate including a redistribution pad extending from a redistribution layer and including segmenting grooves along a redial direction thereof and semiconductor package including the same Apr 11, 2022 Issued
Menu