Search

Rocio Del Mar Perez-velez

Examiner (ID: 14017, Phone: (571)270-5935 , Office: P/2132 )

Most Active Art Unit
2132
Art Unit(s)
2182, 2117, 2187, 2132, 2133, 2100
Total Applications
253
Issued Applications
200
Pending Applications
2
Abandoned Applications
50

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7809016 [patent_doc_number] => 20120059970 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-03-08 [patent_title] => 'MEMORY CONTROLLER SUPPORTING CONCURRENT VOLATILE AND NONVOLATILE MEMORY MODULES IN A MEMORY BUS ARCHITECTURE' [patent_app_type] => utility [patent_app_number] => 13/082383 [patent_app_country] => US [patent_app_date] => 2011-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 13369 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0059/20120059970.pdf [firstpage_image] =>[orig_patent_app_number] => 13082383 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/082383
Memory controller supporting concurrent volatile and nonvolatile memory modules in a memory bus architecture Apr 6, 2011 Issued
Array ( [id] => 9611564 [patent_doc_number] => 08788753 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-07-22 [patent_title] => 'Systems configured for improved storage system communication for N-way interconnectivity' [patent_app_type] => utility [patent_app_number] => 13/082148 [patent_app_country] => US [patent_app_date] => 2011-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 5589 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13082148 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/082148
Systems configured for improved storage system communication for N-way interconnectivity Apr 6, 2011 Issued
Array ( [id] => 8511963 [patent_doc_number] => 20120311371 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-12-06 [patent_title] => 'TIME MULTIPLEXING AT DIFFERENT RATES TO ACCESS DIFFERENT MEMORY TYPES' [patent_app_type] => utility [patent_app_number] => 13/578736 [patent_app_country] => US [patent_app_date] => 2010-11-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 15030 [patent_no_of_claims] => 48 [patent_no_of_ind_claims] => 19 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13578736 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/578736
Time multiplexing at different rates to access different memory types Nov 22, 2010 Issued
Array ( [id] => 6171602 [patent_doc_number] => 20110197038 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-08-11 [patent_title] => 'SERVICING LOW-LATENCY REQUESTS AHEAD OF BEST-EFFORT REQUESTS' [patent_app_type] => utility [patent_app_number] => 12/881963 [patent_app_country] => US [patent_app_date] => 2010-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 9732 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0197/20110197038.pdf [firstpage_image] =>[orig_patent_app_number] => 12881963 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/881963
SERVICING LOW-LATENCY REQUESTS AHEAD OF BEST-EFFORT REQUESTS Sep 13, 2010 Abandoned
Array ( [id] => 9077427 [patent_doc_number] => 08555019 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-10-08 [patent_title] => 'Using a migration cache to cache tracks during migration' [patent_app_type] => utility [patent_app_number] => 12/877956 [patent_app_country] => US [patent_app_date] => 2010-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 5139 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 260 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12877956 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/877956
Using a migration cache to cache tracks during migration Sep 7, 2010 Issued
Array ( [id] => 8678583 [patent_doc_number] => 08386717 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-02-26 [patent_title] => 'Method and apparatus to free up cache memory space with a pseudo least recently used scheme' [patent_app_type] => utility [patent_app_number] => 12/877209 [patent_app_country] => US [patent_app_date] => 2010-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 7665 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12877209 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/877209
Method and apparatus to free up cache memory space with a pseudo least recently used scheme Sep 7, 2010 Issued
Array ( [id] => 9169772 [patent_doc_number] => 08595465 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-11-26 [patent_title] => 'Virtual address to physical address translation using prediction logic' [patent_app_type] => utility [patent_app_number] => 12/877788 [patent_app_country] => US [patent_app_date] => 2010-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6281 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12877788 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/877788
Virtual address to physical address translation using prediction logic Sep 7, 2010 Issued
Array ( [id] => 10854111 [patent_doc_number] => 08880820 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-11-04 [patent_title] => 'Techniques for using sparse files during snapshots' [patent_app_type] => utility [patent_app_number] => 12/877186 [patent_app_country] => US [patent_app_date] => 2010-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3232 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 225 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12877186 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/877186
Techniques for using sparse files during snapshots Sep 7, 2010 Issued
Array ( [id] => 7722008 [patent_doc_number] => 20120011343 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-01-12 [patent_title] => 'DATA PROCESSING APPARATUS AND METHOD' [patent_app_type] => utility [patent_app_number] => 12/876524 [patent_app_country] => US [patent_app_date] => 2010-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2415 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0011/20120011343.pdf [firstpage_image] =>[orig_patent_app_number] => 12876524 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/876524
Data processing apparatus using pre-fetched data Sep 6, 2010 Issued
Array ( [id] => 9012416 [patent_doc_number] => 08527736 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-09-03 [patent_title] => 'Systems and methods for improving address translation speed' [patent_app_type] => utility [patent_app_number] => 12/876844 [patent_app_country] => US [patent_app_date] => 2010-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 11472 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 253 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12876844 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/876844
Systems and methods for improving address translation speed Sep 6, 2010 Issued
Array ( [id] => 7809022 [patent_doc_number] => 20120059976 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-03-08 [patent_title] => 'STORAGE ARRAY CONTROLLER FOR SOLID-STATE STORAGE DEVICES' [patent_app_type] => utility [patent_app_number] => 12/876393 [patent_app_country] => US [patent_app_date] => 2010-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 13096 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0059/20120059976.pdf [firstpage_image] =>[orig_patent_app_number] => 12876393 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/876393
STORAGE ARRAY CONTROLLER FOR SOLID-STATE STORAGE DEVICES Sep 6, 2010 Abandoned
Array ( [id] => 9077434 [patent_doc_number] => 08555026 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-10-08 [patent_title] => 'Methods and systems for storing variable width stack elements in a single memory stack' [patent_app_type] => utility [patent_app_number] => 12/876169 [patent_app_country] => US [patent_app_date] => 2010-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3351 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12876169 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/876169
Methods and systems for storing variable width stack elements in a single memory stack Sep 5, 2010 Issued
Array ( [id] => 8752069 [patent_doc_number] => 08417912 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-04-09 [patent_title] => 'Management of low-paging space conditions in an operating system' [patent_app_type] => utility [patent_app_number] => 12/875831 [patent_app_country] => US [patent_app_date] => 2010-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 10164 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 295 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12875831 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/875831
Management of low-paging space conditions in an operating system Sep 2, 2010 Issued
Array ( [id] => 8912360 [patent_doc_number] => 08484436 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-07-09 [patent_title] => 'Processor independent loop entry cache' [patent_app_type] => utility [patent_app_number] => 12/874934 [patent_app_country] => US [patent_app_date] => 2010-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3330 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12874934 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/874934
Processor independent loop entry cache Sep 1, 2010 Issued
Array ( [id] => 7722002 [patent_doc_number] => 20120011337 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-01-12 [patent_title] => 'HETEROGENEOUS REDUNDANT STORAGE ARRAY' [patent_app_type] => utility [patent_app_number] => 12/875073 [patent_app_country] => US [patent_app_date] => 2010-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6091 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0011/20120011337.pdf [firstpage_image] =>[orig_patent_app_number] => 12875073 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/875073
Heterogeneous redundant storage array Sep 1, 2010 Issued
Array ( [id] => 7792890 [patent_doc_number] => 20120054446 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-03-01 [patent_title] => 'IMPLEMENTING CACHE OFFLOADING' [patent_app_type] => utility [patent_app_number] => 12/873780 [patent_app_country] => US [patent_app_date] => 2010-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 2385 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0054/20120054446.pdf [firstpage_image] =>[orig_patent_app_number] => 12873780 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/873780
Implementing cache offloading Aug 31, 2010 Issued
Array ( [id] => 8804866 [patent_doc_number] => 08443149 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-05-14 [patent_title] => 'Evicting data from a cache via a batch file' [patent_app_type] => utility [patent_app_number] => 12/873763 [patent_app_country] => US [patent_app_date] => 2010-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 9667 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 206 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12873763 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/873763
Evicting data from a cache via a batch file Aug 31, 2010 Issued
Array ( [id] => 9169761 [patent_doc_number] => 08595454 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-11-26 [patent_title] => 'System and method for caching mapping information for off-host backups' [patent_app_type] => utility [patent_app_number] => 12/872056 [patent_app_country] => US [patent_app_date] => 2010-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5819 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 222 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12872056 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/872056
System and method for caching mapping information for off-host backups Aug 30, 2010 Issued
Array ( [id] => 8678605 [patent_doc_number] => 08386741 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-02-26 [patent_title] => 'Method and apparatus for optimizing data allocation' [patent_app_type] => utility [patent_app_number] => 12/871970 [patent_app_country] => US [patent_app_date] => 2010-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 7850 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 257 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12871970 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/871970
Method and apparatus for optimizing data allocation Aug 30, 2010 Issued
Array ( [id] => 7582252 [patent_doc_number] => 20110296135 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-12-01 [patent_title] => 'SYSTEM AND METHOD FOR FREEING MEMORY' [patent_app_type] => utility [patent_app_number] => 12/788706 [patent_app_country] => US [patent_app_date] => 2010-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3146 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0296/20110296135.pdf [firstpage_image] =>[orig_patent_app_number] => 12788706 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/788706
System and method for freeing memory May 26, 2010 Issued
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