Search

Rocio Del Mar Perez-velez

Examiner (ID: 4591, Phone: (571)270-5935 , Office: P/2132 )

Most Active Art Unit
2132
Art Unit(s)
2182, 2100, 2187, 2117, 2133, 2132
Total Applications
254
Issued Applications
200
Pending Applications
5
Abandoned Applications
50

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18759801 [patent_doc_number] => 11810838 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-11-07 [patent_title] => Microelectronic devices, and related electronic systems and methods of forming microelectronic devices [patent_app_type] => utility [patent_app_number] => 17/364292 [patent_app_country] => US [patent_app_date] => 2021-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 11612 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17364292 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/364292
Microelectronic devices, and related electronic systems and methods of forming microelectronic devices Jun 29, 2021 Issued
Array ( [id] => 18304452 [patent_doc_number] => 11626366 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-04-11 [patent_title] => Shielding using layers with staggered trenches [patent_app_type] => utility [patent_app_number] => 17/360793 [patent_app_country] => US [patent_app_date] => 2021-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 16 [patent_no_of_words] => 4773 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17360793 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/360793
Shielding using layers with staggered trenches Jun 27, 2021 Issued
Array ( [id] => 18967554 [patent_doc_number] => 11901336 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-02-13 [patent_title] => Semiconductor package [patent_app_type] => utility [patent_app_number] => 17/355874 [patent_app_country] => US [patent_app_date] => 2021-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 10554 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 296 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17355874 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/355874
Semiconductor package Jun 22, 2021 Issued
Array ( [id] => 17303108 [patent_doc_number] => 20210398947 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-23 [patent_title] => CHIP-STACKED SEMICONDUCTOR PACKAGE WITH INCREASED PACKAGE RELIABILITY [patent_app_type] => utility [patent_app_number] => 17/352757 [patent_app_country] => US [patent_app_date] => 2021-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9619 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17352757 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/352757
Chip-stacked semiconductor package with increased package reliability Jun 20, 2021 Issued
Array ( [id] => 19936791 [patent_doc_number] => 12310011 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-05-20 [patent_title] => Three-dimensional memory devices and methods for forming the same [patent_app_type] => utility [patent_app_number] => 17/352242 [patent_app_country] => US [patent_app_date] => 2021-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 26 [patent_no_of_words] => 10929 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17352242 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/352242
Three-dimensional memory devices and methods for forming the same Jun 17, 2021 Issued
Array ( [id] => 18304462 [patent_doc_number] => 11626376 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-04-11 [patent_title] => Semiconductor device having a plurality of first structural bodies provided below a connection terminal and manufacturing method thereof [patent_app_type] => utility [patent_app_number] => 17/350899 [patent_app_country] => US [patent_app_date] => 2021-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 27 [patent_no_of_words] => 9874 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 194 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17350899 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/350899
Semiconductor device having a plurality of first structural bodies provided below a connection terminal and manufacturing method thereof Jun 16, 2021 Issued
Array ( [id] => 17130637 [patent_doc_number] => 20210305406 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-30 [patent_title] => SAWTOOH ELECTRIC FIELD DRIFT REGION STRUCTURE FOR PLANAR AND TRENCH POWER SEMICONDUCTOR DEVICES [patent_app_type] => utility [patent_app_number] => 17/346271 [patent_app_country] => US [patent_app_date] => 2021-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7205 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17346271 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/346271
Sawtooh electric field drift region structure for planar and trench power semiconductor devices Jun 12, 2021 Issued
Array ( [id] => 17582985 [patent_doc_number] => 20220139840 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-05 [patent_title] => THROUGH-SILICON VIA (TSV) KEY FOR OVERLAY MEASUREMENT, AND SEMICONDUCTOR DEVICE AND SEMICONDUCTOR PACKAGE INCLUDING TSV KEY [patent_app_type] => utility [patent_app_number] => 17/340445 [patent_app_country] => US [patent_app_date] => 2021-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12521 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17340445 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/340445
Through-silicon via (TSV) key for overlay measurement, and semiconductor device and semiconductor package including TSV key Jun 6, 2021 Issued
Array ( [id] => 17115578 [patent_doc_number] => 20210296175 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-23 [patent_title] => INORGANIC DIES WITH ORGANIC INTERCONNECT LAYERS AND RELATED STRUCTURES [patent_app_type] => utility [patent_app_number] => 17/338296 [patent_app_country] => US [patent_app_date] => 2021-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19049 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17338296 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/338296
Inorganic dies with organic interconnect layers and related structures Jun 2, 2021 Issued
Array ( [id] => 18578994 [patent_doc_number] => 11735534 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-22 [patent_title] => Chip package and method of forming a chip package [patent_app_type] => utility [patent_app_number] => 17/333186 [patent_app_country] => US [patent_app_date] => 2021-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 4697 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17333186 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/333186
Chip package and method of forming a chip package May 27, 2021 Issued
Array ( [id] => 18317547 [patent_doc_number] => 11631631 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-04-18 [patent_title] => Semiconductor device including via structure for vertical electrical connection [patent_app_type] => utility [patent_app_number] => 17/334571 [patent_app_country] => US [patent_app_date] => 2021-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 7292 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17334571 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/334571
Semiconductor device including via structure for vertical electrical connection May 27, 2021 Issued
Array ( [id] => 18040062 [patent_doc_number] => 20220384279 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-01 [patent_title] => TEST LINE STRUCTURE, SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING TEST LINE STRUCTURE [patent_app_type] => utility [patent_app_number] => 17/331675 [patent_app_country] => US [patent_app_date] => 2021-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8711 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17331675 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/331675
Test line structure, semiconductor structure and method for forming test line structure May 26, 2021 Issued
Array ( [id] => 18129679 [patent_doc_number] => 11555883 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-01-17 [patent_title] => Noise measurement in a radar system [patent_app_type] => utility [patent_app_number] => 17/331419 [patent_app_country] => US [patent_app_date] => 2021-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 7100 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17331419 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/331419
Noise measurement in a radar system May 25, 2021 Issued
Array ( [id] => 18040190 [patent_doc_number] => 20220384407 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-01 [patent_title] => COPPER-BONDED MEMORY STACKS WITH COPPER-BONDED INTERCONNECTION MEMORY SYSTEMS [patent_app_type] => utility [patent_app_number] => 17/331196 [patent_app_country] => US [patent_app_date] => 2021-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4999 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 21 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17331196 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/331196
Copper-bonded memory stacks with copper-bonded interconnection memory systems May 25, 2021 Issued
Array ( [id] => 17085534 [patent_doc_number] => 20210280541 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-09 [patent_title] => SEMICONDUCTOR DEVICES INCLUDING A THICK METAL LAYER AND A BUMP [patent_app_type] => utility [patent_app_number] => 17/328365 [patent_app_country] => US [patent_app_date] => 2021-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8727 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17328365 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/328365
Semiconductor devices including a thick metal layer and a bump May 23, 2021 Issued
Array ( [id] => 18131389 [patent_doc_number] => 11557606 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-01-17 [patent_title] => Epitaxial monocrystalline channel for storage transistors in 3-dimensional memory structures and methods for formation thereof [patent_app_type] => utility [patent_app_number] => 17/329007 [patent_app_country] => US [patent_app_date] => 2021-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 16 [patent_no_of_words] => 2720 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 221 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17329007 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/329007
Epitaxial monocrystalline channel for storage transistors in 3-dimensional memory structures and methods for formation thereof May 23, 2021 Issued
Array ( [id] => 18131355 [patent_doc_number] => 11557572 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-01-17 [patent_title] => Semiconductor device with stacked dies and method for fabricating the same [patent_app_type] => utility [patent_app_number] => 17/319257 [patent_app_country] => US [patent_app_date] => 2021-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 10761 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 403 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17319257 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/319257
Semiconductor device with stacked dies and method for fabricating the same May 12, 2021 Issued
Array ( [id] => 18105577 [patent_doc_number] => 11545475 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-01-03 [patent_title] => Integrated display devices [patent_app_type] => utility [patent_app_number] => 17/318736 [patent_app_country] => US [patent_app_date] => 2021-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 16 [patent_no_of_words] => 11077 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17318736 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/318736
Integrated display devices May 11, 2021 Issued
Array ( [id] => 18190637 [patent_doc_number] => 11581238 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-02-14 [patent_title] => Heat spreading layer integrated within a composite IC die structure and methods of forming the same [patent_app_type] => utility [patent_app_number] => 17/318887 [patent_app_country] => US [patent_app_date] => 2021-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 17 [patent_no_of_words] => 9260 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17318887 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/318887
Heat spreading layer integrated within a composite IC die structure and methods of forming the same May 11, 2021 Issued
Array ( [id] => 17993445 [patent_doc_number] => 20220359482 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-10 [patent_title] => MEMORY AND LOGIC CHIP STACK WITH A TRANSLATOR CHIP [patent_app_type] => utility [patent_app_number] => 17/315965 [patent_app_country] => US [patent_app_date] => 2021-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9068 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17315965 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/315965
Memory and logic chip stack with a translator chip May 9, 2021 Issued
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