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Rocio Del Mar Perez-velez

Examiner (ID: 4591, Phone: (571)270-5935 , Office: P/2132 )

Most Active Art Unit
2132
Art Unit(s)
2182, 2100, 2187, 2117, 2133, 2132
Total Applications
254
Issued Applications
200
Pending Applications
5
Abandoned Applications
50

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18088639 [patent_doc_number] => 11538778 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-12-27 [patent_title] => Semiconductor package including alignment material and method for manufacturing semiconductor package [patent_app_type] => utility [patent_app_number] => 17/127671 [patent_app_country] => US [patent_app_date] => 2020-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 28 [patent_no_of_words] => 10177 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17127671 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/127671
Semiconductor package including alignment material and method for manufacturing semiconductor package Dec 17, 2020 Issued
Array ( [id] => 17818597 [patent_doc_number] => 11424221 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-08-23 [patent_title] => Pad structures for semiconductor devices [patent_app_type] => utility [patent_app_number] => 17/127019 [patent_app_country] => US [patent_app_date] => 2020-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6677 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17127019 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/127019
Pad structures for semiconductor devices Dec 17, 2020 Issued
Array ( [id] => 17730816 [patent_doc_number] => 11387218 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-07-12 [patent_title] => Pad-out structure for semiconductor device and method of forming the same [patent_app_type] => utility [patent_app_number] => 17/127083 [patent_app_country] => US [patent_app_date] => 2020-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 5543 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17127083 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/127083
Pad-out structure for semiconductor device and method of forming the same Dec 17, 2020 Issued
Array ( [id] => 16752486 [patent_doc_number] => 20210104498 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-08 [patent_title] => SEMICONDUCTOR DIE FOR DETERMINING LOAD OF THROUGH SILICON VIA AND SEMICONDUCTOR DEVICE INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 17/124762 [patent_app_country] => US [patent_app_date] => 2020-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11173 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17124762 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/124762
Semiconductor die for determining load of through silicon via and semiconductor device including the same Dec 16, 2020 Issued
Array ( [id] => 16751015 [patent_doc_number] => 20210103024 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-08 [patent_title] => Polarization Axis Attenuation and Cross Polarization Resistant Antenna Orientation Assembly for Tracked Object [patent_app_type] => utility [patent_app_number] => 17/125215 [patent_app_country] => US [patent_app_date] => 2020-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4503 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17125215 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/125215
Polarization axis attenuation and cross polarization resistant antenna orientation assembly for tracked object Dec 16, 2020 Issued
Array ( [id] => 17978663 [patent_doc_number] => 11495535 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-11-08 [patent_title] => Fuses to measure electrostatic discharge during die to substrate or package assembly [patent_app_type] => utility [patent_app_number] => 17/124801 [patent_app_country] => US [patent_app_date] => 2020-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4920 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17124801 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/124801
Fuses to measure electrostatic discharge during die to substrate or package assembly Dec 16, 2020 Issued
Array ( [id] => 18833888 [patent_doc_number] => 20230402415 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-14 [patent_title] => METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 18/252891 [patent_app_country] => US [patent_app_date] => 2020-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10702 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 209 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18252891 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/252891
METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE Dec 16, 2020 Pending
Array ( [id] => 17676755 [patent_doc_number] => 20220189922 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-16 [patent_title] => CREATE A PROTECTED LAYER FOR INTERCONNECTS AND DEVICES IN A PACKAGED QUANTUM STRUCTURE [patent_app_type] => utility [patent_app_number] => 17/123350 [patent_app_country] => US [patent_app_date] => 2020-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9576 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17123350 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/123350
Create a protected layer for interconnects and devices in a packaged quantum structure Dec 15, 2020 Issued
Array ( [id] => 17676730 [patent_doc_number] => 20220189897 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-16 [patent_title] => HIGH-SPEED DIE CONNECTIONS USING A CONDUCTIVE INSERT [patent_app_type] => utility [patent_app_number] => 17/118126 [patent_app_country] => US [patent_app_date] => 2020-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5442 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17118126 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/118126
High-speed die connections using a conductive insert Dec 9, 2020 Issued
Array ( [id] => 17660815 [patent_doc_number] => 20220181280 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-09 [patent_title] => MOLDED SEMICONDUCTOR PACKAGE WITH HIGH VOLTAGE ISOLATION [patent_app_type] => utility [patent_app_number] => 17/113170 [patent_app_country] => US [patent_app_date] => 2020-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5727 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17113170 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/113170
Molded semiconductor package with high voltage isolation Dec 6, 2020 Issued
Array ( [id] => 16721500 [patent_doc_number] => 20210088647 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-25 [patent_title] => Tailoring Sensor Emission Power to Map, Vehicle State, and Environment [patent_app_type] => utility [patent_app_number] => 17/110762 [patent_app_country] => US [patent_app_date] => 2020-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11507 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17110762 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/110762
Tailoring sensor emission power to map, vehicle state, and environment Dec 2, 2020 Issued
Array ( [id] => 18032036 [patent_doc_number] => 11515234 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-11-29 [patent_title] => Semiconductor device package including promoters and method of manufacturing the same [patent_app_type] => utility [patent_app_number] => 17/111335 [patent_app_country] => US [patent_app_date] => 2020-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 4073 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 43 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17111335 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/111335
Semiconductor device package including promoters and method of manufacturing the same Dec 2, 2020 Issued
Array ( [id] => 19139489 [patent_doc_number] => 11974482 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-30 [patent_title] => Display substrate and related devices [patent_app_type] => utility [patent_app_number] => 17/435917 [patent_app_country] => US [patent_app_date] => 2020-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 14117 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 303 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17435917 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/435917
Display substrate and related devices Nov 29, 2020 Issued
Array ( [id] => 19796323 [patent_doc_number] => 12237292 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-02-25 [patent_title] => Circuits including micropatterns and using partial curing to adhere dies [patent_app_type] => utility [patent_app_number] => 17/756208 [patent_app_country] => US [patent_app_date] => 2020-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 7602 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17756208 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/756208
Circuits including micropatterns and using partial curing to adhere dies Nov 29, 2020 Issued
Array ( [id] => 16873527 [patent_doc_number] => 20210166994 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-03 [patent_title] => SEMICONDUCTOR WAFER AND SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 17/103887 [patent_app_country] => US [patent_app_date] => 2020-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7069 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17103887 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/103887
Semiconductor wafer and semiconductor device for suppressing the propagation of cracks Nov 23, 2020 Issued
Array ( [id] => 16692206 [patent_doc_number] => 20210074685 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-11 [patent_title] => MEMORY DEVICE, SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 17/102104 [patent_app_country] => US [patent_app_date] => 2020-11-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6519 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17102104 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/102104
Multilayered memory device with through-silicon via(TSV), semiconductor device and method for manufacturing the same Nov 22, 2020 Issued
Array ( [id] => 17188851 [patent_doc_number] => 20210335736 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-10-28 [patent_title] => SEMICONDUCTOR PACKAGE [patent_app_type] => utility [patent_app_number] => 17/101443 [patent_app_country] => US [patent_app_date] => 2020-11-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6247 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17101443 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/101443
Semiconductor package including dummy bump Nov 22, 2020 Issued
Array ( [id] => 18729437 [patent_doc_number] => 20230343733 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-26 [patent_title] => WAFER BONDING STRUCTURE, WAFER BONDING METHOD AND CHIP BONDING STRUCTURE [patent_app_type] => utility [patent_app_number] => 18/014009 [patent_app_country] => US [patent_app_date] => 2020-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5601 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18014009 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/014009
WAFER BONDING STRUCTURE, WAFER BONDING METHOD AND CHIP BONDING STRUCTURE Nov 16, 2020 Issued
Array ( [id] => 16689893 [patent_doc_number] => 20210072370 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-11 [patent_title] => Radar-Based Gesture Enhancement for Voice Interfaces [patent_app_type] => utility [patent_app_number] => 16/950248 [patent_app_country] => US [patent_app_date] => 2020-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14273 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16950248 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/950248
Radar-based gesture enhancement for voice interfaces Nov 16, 2020 Issued
Array ( [id] => 17818591 [patent_doc_number] => 11424215 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-08-23 [patent_title] => Bonded assembly formed by hybrid wafer bonding using selectively deposited metal liners [patent_app_type] => utility [patent_app_number] => 17/094543 [patent_app_country] => US [patent_app_date] => 2020-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 8832 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 204 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17094543 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/094543
Bonded assembly formed by hybrid wafer bonding using selectively deposited metal liners Nov 9, 2020 Issued
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