Search

Rocio Del Mar Perez-velez

Examiner (ID: 4591, Phone: (571)270-5935 , Office: P/2132 )

Most Active Art Unit
2132
Art Unit(s)
2182, 2100, 2187, 2117, 2133, 2132
Total Applications
254
Issued Applications
200
Pending Applications
5
Abandoned Applications
50

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 10125583 [patent_doc_number] => 09159955 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-10-13 [patent_title] => 'Method and apparatus for patterning an organic device' [patent_app_type] => utility [patent_app_number] => 14/245218 [patent_app_country] => US [patent_app_date] => 2014-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 10110 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14245218 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/245218
Method and apparatus for patterning an organic device Apr 3, 2014 Issued
Array ( [id] => 9631743 [patent_doc_number] => 20140209851 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-07-31 [patent_title] => 'Memory Cell Constructions, and Methods for Fabricating Memory Cell Constructions' [patent_app_type] => utility [patent_app_number] => 14/243710 [patent_app_country] => US [patent_app_date] => 2014-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4110 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14243710 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/243710
Memory cell constructions, and methods for fabricating memory cell constructions Apr 1, 2014 Issued
Array ( [id] => 10329149 [patent_doc_number] => 20150214153 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-07-30 [patent_title] => 'SEMICONDUCTOR APPARATUS' [patent_app_type] => utility [patent_app_number] => 14/243564 [patent_app_country] => US [patent_app_date] => 2014-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4260 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14243564 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/243564
Power line structure for semiconductor apparatus Apr 1, 2014 Issued
Array ( [id] => 10502692 [patent_doc_number] => 09231095 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-01-05 [patent_title] => 'Method for manufacturing semiconductor device' [patent_app_type] => utility [patent_app_number] => 14/221489 [patent_app_country] => US [patent_app_date] => 2014-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 15 [patent_no_of_words] => 3615 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14221489 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/221489
Method for manufacturing semiconductor device Mar 20, 2014 Issued
Array ( [id] => 9668063 [patent_doc_number] => 20140231927 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-08-21 [patent_title] => 'SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 14/217091 [patent_app_country] => US [patent_app_date] => 2014-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 33 [patent_figures_cnt] => 33 [patent_no_of_words] => 7176 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14217091 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/217091
Semiconductor device and manufacturing method thereof Mar 16, 2014 Issued
Array ( [id] => 9603139 [patent_doc_number] => 20140199821 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-07-17 [patent_title] => 'VARIABLE-RESISTANCE MATERIAL MEMORIES AND METHODS' [patent_app_type] => utility [patent_app_number] => 14/216068 [patent_app_country] => US [patent_app_date] => 2014-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 5564 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14216068 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/216068
Variable-resistance material memories and methods Mar 16, 2014 Issued
Array ( [id] => 11286523 [patent_doc_number] => 09502383 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-11-22 [patent_title] => '3D integrated circuit package processing with panel type lid' [patent_app_type] => utility [patent_app_number] => 14/206870 [patent_app_country] => US [patent_app_date] => 2014-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 4548 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14206870 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/206870
3D integrated circuit package processing with panel type lid Mar 11, 2014 Issued
Array ( [id] => 10631530 [patent_doc_number] => 09349686 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-05-24 [patent_title] => 'Reduced height M1 metal lines for local on-chip routing' [patent_app_type] => utility [patent_app_number] => 14/206360 [patent_app_country] => US [patent_app_date] => 2014-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3749 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14206360 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/206360
Reduced height M1 metal lines for local on-chip routing Mar 11, 2014 Issued
Array ( [id] => 9597282 [patent_doc_number] => 20140193962 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-07-10 [patent_title] => 'SEMICONDUCTOR DEVICES AND METHODS OF FORMING THE SAME' [patent_app_type] => utility [patent_app_number] => 14/202629 [patent_app_country] => US [patent_app_date] => 2014-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6729 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14202629 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/202629
Semiconductor devices and methods of forming the same Mar 9, 2014 Issued
Array ( [id] => 10370391 [patent_doc_number] => 20150255396 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-09-10 [patent_title] => 'SEMICONDUCTOR DEVICE AND FORMATION THEREOF' [patent_app_type] => utility [patent_app_number] => 14/200247 [patent_app_country] => US [patent_app_date] => 2014-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4063 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14200247 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/200247
Semiconductor device comprising metal plug having substantially convex bottom surface Mar 6, 2014 Issued
Array ( [id] => 10016289 [patent_doc_number] => 09059311 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-06-16 [patent_title] => 'CMOS transistors with identical active semiconductor region shapes' [patent_app_type] => utility [patent_app_number] => 14/197631 [patent_app_country] => US [patent_app_date] => 2014-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 36 [patent_no_of_words] => 7731 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14197631 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/197631
CMOS transistors with identical active semiconductor region shapes Mar 4, 2014 Issued
Array ( [id] => 9561345 [patent_doc_number] => 20140179059 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-06-26 [patent_title] => 'PACKAGE-LEVEL INTEGRATED CIRCUIT CONNECTION WITHOUT TOP METAL PADS OR BONDING WIRE' [patent_app_type] => utility [patent_app_number] => 14/193436 [patent_app_country] => US [patent_app_date] => 2014-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1804 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14193436 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/193436
PACKAGE-LEVEL INTEGRATED CIRCUIT CONNECTION WITHOUT TOP METAL PADS OR BONDING WIRE Feb 27, 2014 Abandoned
Array ( [id] => 9844807 [patent_doc_number] => 08946725 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-02-03 [patent_title] => 'Vertical gallium nitride JFET with gate and source electrodes on regrown gate' [patent_app_type] => utility [patent_app_number] => 14/192662 [patent_app_country] => US [patent_app_date] => 2014-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 6512 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14192662 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/192662
Vertical gallium nitride JFET with gate and source electrodes on regrown gate Feb 26, 2014 Issued
Array ( [id] => 9869723 [patent_doc_number] => 08957497 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-02-17 [patent_title] => 'Vertically integrated systems' [patent_app_type] => utility [patent_app_number] => 14/189788 [patent_app_country] => US [patent_app_date] => 2014-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 41 [patent_figures_cnt] => 71 [patent_no_of_words] => 14585 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14189788 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/189788
Vertically integrated systems Feb 24, 2014 Issued
Array ( [id] => 9995775 [patent_doc_number] => 09040370 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-05-26 [patent_title] => 'Anti-fuses on semiconductor fins' [patent_app_type] => utility [patent_app_number] => 14/189655 [patent_app_country] => US [patent_app_date] => 2014-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 3403 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14189655 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/189655
Anti-fuses on semiconductor fins Feb 24, 2014 Issued
Array ( [id] => 9557888 [patent_doc_number] => 20140175600 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-06-26 [patent_title] => 'VERTICALLY INTEGRATED SYSTEMS' [patent_app_type] => utility [patent_app_number] => 14/189805 [patent_app_country] => US [patent_app_date] => 2014-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 42 [patent_figures_cnt] => 42 [patent_no_of_words] => 14585 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14189805 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/189805
Vertically integrated systems Feb 24, 2014 Issued
Array ( [id] => 10125450 [patent_doc_number] => 09159819 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-10-13 [patent_title] => 'Semiconductor device and RC-IGBT with zones directly adjoining a rear side electrode' [patent_app_type] => utility [patent_app_number] => 14/185117 [patent_app_country] => US [patent_app_date] => 2014-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 17 [patent_no_of_words] => 8823 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14185117 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/185117
Semiconductor device and RC-IGBT with zones directly adjoining a rear side electrode Feb 19, 2014 Issued
Array ( [id] => 9832431 [patent_doc_number] => 08941250 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-01-27 [patent_title] => 'Electronic component package fabrication method and structure' [patent_app_type] => utility [patent_app_number] => 14/182083 [patent_app_country] => US [patent_app_date] => 2014-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3751 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14182083 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/182083
Electronic component package fabrication method and structure Feb 16, 2014 Issued
Array ( [id] => 9990127 [patent_doc_number] => 09035334 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-05-19 [patent_title] => 'Method and apparatus for fabricating phosphor-coated LED dies' [patent_app_type] => utility [patent_app_number] => 14/174929 [patent_app_country] => US [patent_app_date] => 2014-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 5972 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 42 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14174929 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/174929
Method and apparatus for fabricating phosphor-coated LED dies Feb 6, 2014 Issued
Array ( [id] => 10125368 [patent_doc_number] => 09159736 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-10-13 [patent_title] => 'Data line arrangement and pillar arrangement in apparatuses' [patent_app_type] => utility [patent_app_number] => 14/175901 [patent_app_country] => US [patent_app_date] => 2014-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 5066 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14175901 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/175901
Data line arrangement and pillar arrangement in apparatuses Feb 6, 2014 Issued
Menu