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Rocio Del Mar Perez-velez

Examiner (ID: 4591, Phone: (571)270-5935 , Office: P/2132 )

Most Active Art Unit
2132
Art Unit(s)
2182, 2100, 2187, 2117, 2133, 2132
Total Applications
254
Issued Applications
200
Pending Applications
5
Abandoned Applications
50

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 9508765 [patent_doc_number] => 20140145256 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-05-29 [patent_title] => 'ELECTRONIC DEVICE COMPRISING A CONDUCTIVE STRUCTURE AND AN INSULATING LAYER WITHIN A TRENCH' [patent_app_type] => utility [patent_app_number] => 14/171427 [patent_app_country] => US [patent_app_date] => 2014-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 11177 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14171427 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/171427
Electronic device comprising a conductive structure and an insulating layer within a trench Feb 2, 2014 Issued
Array ( [id] => 9824013 [patent_doc_number] => 08933501 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-01-13 [patent_title] => 'Three dimensional NAND device and method of charge trap layer separation and floating gate formation in the NAND device' [patent_app_type] => utility [patent_app_number] => 14/166162 [patent_app_country] => US [patent_app_date] => 2014-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 26 [patent_no_of_words] => 6360 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 215 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14166162 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/166162
Three dimensional NAND device and method of charge trap layer separation and floating gate formation in the NAND device Jan 27, 2014 Issued
Array ( [id] => 10132109 [patent_doc_number] => 09165950 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-10-20 [patent_title] => 'Anti-static structure of array substrate' [patent_app_type] => utility [patent_app_number] => 14/347596 [patent_app_country] => US [patent_app_date] => 2014-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 3529 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14347596 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/347596
Anti-static structure of array substrate Jan 20, 2014 Issued
Array ( [id] => 10302830 [patent_doc_number] => 20150187830 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-07-02 [patent_title] => 'PHOTOSENSITIVE UNIT, ARRAY SUBSTRATE OF DISPLAY PANEL AND MANUFACTURING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 14/240361 [patent_app_country] => US [patent_app_date] => 2014-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3282 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14240361 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/240361
PHOTOSENSITIVE UNIT, ARRAY SUBSTRATE OF DISPLAY PANEL AND MANUFACTURING METHOD THEREOF Jan 19, 2014 Abandoned
Array ( [id] => 10252132 [patent_doc_number] => 20150137128 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-05-21 [patent_title] => 'THIN-FILM TRANSISTOR ARRAY SUBSTRATE AND METHOD FOR REPAIRING THE SAME' [patent_app_type] => utility [patent_app_number] => 14/241392 [patent_app_country] => US [patent_app_date] => 2014-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3224 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14241392 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/241392
THIN-FILM TRANSISTOR ARRAY SUBSTRATE AND METHOD FOR REPAIRING THE SAME Jan 16, 2014 Abandoned
Array ( [id] => 10831184 [patent_doc_number] => 08859350 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-10-14 [patent_title] => 'Recessed gate field effect transistor' [patent_app_type] => utility [patent_app_number] => 14/157947 [patent_app_country] => US [patent_app_date] => 2014-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 11121 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14157947 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/157947
Recessed gate field effect transistor Jan 16, 2014 Issued
Array ( [id] => 10302891 [patent_doc_number] => 20150187891 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-07-02 [patent_title] => 'Formation of Gate Sidewall Structure' [patent_app_type] => utility [patent_app_number] => 14/143317 [patent_app_country] => US [patent_app_date] => 2013-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 7015 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14143317 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/143317
Formation of gate sidewall structure Dec 29, 2013 Issued
Array ( [id] => 10178813 [patent_doc_number] => 09209025 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-12-08 [patent_title] => 'Low temperature poly-silicon thin film, method for making the thin film, and transistor made from the thin film' [patent_app_type] => utility [patent_app_number] => 14/234985 [patent_app_country] => US [patent_app_date] => 2013-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 2765 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14234985 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/234985
Low temperature poly-silicon thin film, method for making the thin film, and transistor made from the thin film Dec 29, 2013 Issued
Array ( [id] => 10010587 [patent_doc_number] => 09054113 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-06-09 [patent_title] => 'Box-in-box overlay mark' [patent_app_type] => utility [patent_app_number] => 14/142925 [patent_app_country] => US [patent_app_date] => 2013-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 1899 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14142925 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/142925
Box-in-box overlay mark Dec 29, 2013 Issued
Array ( [id] => 10145059 [patent_doc_number] => 09177871 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-11-03 [patent_title] => 'Balancing asymmetric spacers' [patent_app_type] => utility [patent_app_number] => 14/143362 [patent_app_country] => US [patent_app_date] => 2013-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 11438 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14143362 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/143362
Balancing asymmetric spacers Dec 29, 2013 Issued
Array ( [id] => 10302622 [patent_doc_number] => 20150187622 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-07-02 [patent_title] => 'METHODS AND DEVICES FOR SECURING AND TRANSPORTING SINGULATED DIE IN HIGH VOLUME MANUFACTURING' [patent_app_type] => utility [patent_app_number] => 14/142761 [patent_app_country] => US [patent_app_date] => 2013-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7737 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14142761 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/142761
Methods and devices for securing and transporting singulated die in high volume manufacturing Dec 27, 2013 Issued
Array ( [id] => 10534675 [patent_doc_number] => 09260294 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-02-16 [patent_title] => 'Integration of pressure or inertial sensors into integrated circuit fabrication and packaging' [patent_app_type] => utility [patent_app_number] => 14/141875 [patent_app_country] => US [patent_app_date] => 2013-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 69 [patent_no_of_words] => 9445 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14141875 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/141875
Integration of pressure or inertial sensors into integrated circuit fabrication and packaging Dec 26, 2013 Issued
Array ( [id] => 9418722 [patent_doc_number] => 20140103372 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-04-17 [patent_title] => 'METHOD AND APPARATUS FOR PACKAGING PHOSPHOR-COATED LEDS' [patent_app_type] => utility [patent_app_number] => 14/140973 [patent_app_country] => US [patent_app_date] => 2013-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 8150 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14140973 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/140973
Method and apparatus for packaging phosphor-coated LEDs Dec 25, 2013 Issued
Array ( [id] => 10294508 [patent_doc_number] => 20150179507 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-06-25 [patent_title] => 'METHODS FOR PROCESSING A SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 14/138158 [patent_app_country] => US [patent_app_date] => 2013-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5111 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14138158 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/138158
Method for providing a self-aligned pad protection in a semiconductor device Dec 22, 2013 Issued
Array ( [id] => 9812607 [patent_doc_number] => 20150024552 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-01-22 [patent_title] => 'SUBSTRATE, CHIP PACKAGE AND METHOD FOR MANUFACTURING SUBSTRATE' [patent_app_type] => utility [patent_app_number] => 14/139790 [patent_app_country] => US [patent_app_date] => 2013-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 2747 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14139790 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/139790
Substrate, chip package and method for manufacturing substrate Dec 22, 2013 Issued
Array ( [id] => 10294445 [patent_doc_number] => 20150179444 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-06-25 [patent_title] => 'Methods for Forming Crystalline IGZO Through Power Supply Mode Optimization' [patent_app_type] => utility [patent_app_number] => 14/139195 [patent_app_country] => US [patent_app_date] => 2013-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4043 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14139195 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/139195
Methods for Forming Crystalline IGZO Through Power Supply Mode Optimization Dec 22, 2013 Abandoned
Array ( [id] => 10967616 [patent_doc_number] => 20140370649 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-12-18 [patent_title] => 'METHOD AND APPARATUS FOR FORMING COPPER(Cu) OR ANTIMONY(Sb) DOPED ZINC TELLURIDE AND CADMIUM ZINC TELLURIDE LAYERS IN A PHOTOVOLTAIC DEVICE' [patent_app_type] => utility [patent_app_number] => 14/136630 [patent_app_country] => US [patent_app_date] => 2013-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8117 [patent_no_of_claims] => 42 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14136630 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/136630
Method and apparatus for forming copper(Cu) or antimony(Sb) doped zinc telluride and cadmium zinc telluride layers in a photovoltaic device Dec 19, 2013 Issued
Array ( [id] => 10015969 [patent_doc_number] => 09058990 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-06-16 [patent_title] => 'Controlled spalling of group III nitrides containing an embedded spall releasing plane' [patent_app_type] => utility [patent_app_number] => 14/134621 [patent_app_country] => US [patent_app_date] => 2013-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 9501 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14134621 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/134621
Controlled spalling of group III nitrides containing an embedded spall releasing plane Dec 18, 2013 Issued
Array ( [id] => 10060124 [patent_doc_number] => 09099488 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-08-04 [patent_title] => 'Methods to characterize an embedded interface of a CMOS gate stack' [patent_app_type] => utility [patent_app_number] => 14/134291 [patent_app_country] => US [patent_app_date] => 2013-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 27 [patent_no_of_words] => 12966 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 264 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14134291 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/134291
Methods to characterize an embedded interface of a CMOS gate stack Dec 18, 2013 Issued
Array ( [id] => 10125581 [patent_doc_number] => 09159952 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-10-13 [patent_title] => 'Flexible packaging substrate and fabricating method thereof and packaging method for OLED using the same' [patent_app_type] => utility [patent_app_number] => 14/134630 [patent_app_country] => US [patent_app_date] => 2013-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 3294 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14134630 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/134630
Flexible packaging substrate and fabricating method thereof and packaging method for OLED using the same Dec 18, 2013 Issued
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