Search

Rocio Del Mar Perez-velez

Examiner (ID: 4591, Phone: (571)270-5935 , Office: P/2132 )

Most Active Art Unit
2132
Art Unit(s)
2182, 2100, 2187, 2117, 2133, 2132
Total Applications
254
Issued Applications
200
Pending Applications
5
Abandoned Applications
50

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 9888835 [patent_doc_number] => 08975089 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-03-10 [patent_title] => 'Method for forming MTJ memory element' [patent_app_type] => utility [patent_app_number] => 14/082400 [patent_app_country] => US [patent_app_date] => 2013-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 2855 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14082400 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/082400
Method for forming MTJ memory element Nov 17, 2013 Issued
Array ( [id] => 9367508 [patent_doc_number] => 20140077381 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-03-20 [patent_title] => 'Semiconductor Device and Method of Forming FO-WLCSP with Multiple Encapsulants' [patent_app_type] => utility [patent_app_number] => 14/080609 [patent_app_country] => US [patent_app_date] => 2013-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 13218 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14080609 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/080609
Semiconductor device and method of forming FO-WLCSP with multiple encapsulants Nov 13, 2013 Issued
Array ( [id] => 10010579 [patent_doc_number] => 09054106 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-06-09 [patent_title] => 'Semiconductor structure and method for manufacturing the same' [patent_app_type] => utility [patent_app_number] => 14/078653 [patent_app_country] => US [patent_app_date] => 2013-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 1448 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14078653 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/078653
Semiconductor structure and method for manufacturing the same Nov 12, 2013 Issued
Array ( [id] => 10165281 [patent_doc_number] => 09196510 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-11-24 [patent_title] => 'Semiconductor package comprising two semiconductor modules and laterally extending connectors' [patent_app_type] => utility [patent_app_number] => 14/077694 [patent_app_country] => US [patent_app_date] => 2013-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5257 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14077694 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/077694
Semiconductor package comprising two semiconductor modules and laterally extending connectors Nov 11, 2013 Issued
Array ( [id] => 9360337 [patent_doc_number] => 20140070210 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-03-13 [patent_title] => 'OXIDE THIN FILM TRANSISTOR AND METHOD OF FABRICATING THE SAME' [patent_app_type] => utility [patent_app_number] => 14/077319 [patent_app_country] => US [patent_app_date] => 2013-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5387 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14077319 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/077319
Oxide thin film transistor and method of fabricating the same Nov 11, 2013 Issued
Array ( [id] => 10066778 [patent_doc_number] => 09105638 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-08-11 [patent_title] => 'Via-fuse with low dielectric constant' [patent_app_type] => utility [patent_app_number] => 14/076333 [patent_app_country] => US [patent_app_date] => 2013-11-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 14 [patent_no_of_words] => 2336 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14076333 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/076333
Via-fuse with low dielectric constant Nov 10, 2013 Issued
Array ( [id] => 9989564 [patent_doc_number] => 09034767 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-05-19 [patent_title] => 'Facilitating mask pattern formation' [patent_app_type] => utility [patent_app_number] => 14/076386 [patent_app_country] => US [patent_app_date] => 2013-11-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 14 [patent_no_of_words] => 5686 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14076386 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/076386
Facilitating mask pattern formation Nov 10, 2013 Issued
Array ( [id] => 10245071 [patent_doc_number] => 20150130066 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-05-14 [patent_title] => 'INTEGRATED CIRCUIT DEVICE WITH A CONNECTOR ACCESS REGION AND METHOD FOR MAKING THEREOF' [patent_app_type] => utility [patent_app_number] => 14/076376 [patent_app_country] => US [patent_app_date] => 2013-11-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 2308 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14076376 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/076376
Integrated circuit device with a connector access region and method for making thereof Nov 10, 2013 Issued
Array ( [id] => 10309617 [patent_doc_number] => 20150194618 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-07-09 [patent_title] => 'FLEXIBLE ORGANIC LIGHT EMITTING DIODE DISPLAY DEVICE AND MANUFACTURING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 14/353200 [patent_app_country] => US [patent_app_date] => 2013-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3626 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14353200 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/353200
Flexible organic light emitting diode display device and manufacturing method thereof Oct 31, 2013 Issued
Array ( [id] => 10233870 [patent_doc_number] => 20150118864 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-04-30 [patent_title] => 'Method for Treating SiOCH Film With Hydrogen Plasma' [patent_app_type] => utility [patent_app_number] => 14/069244 [patent_app_country] => US [patent_app_date] => 2013-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5639 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14069244 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/069244
Method for treating SiOCH film with hydrogen plasma Oct 30, 2013 Issued
Array ( [id] => 10394902 [patent_doc_number] => 20150279909 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-10-01 [patent_title] => 'ORGANIC ELECTROLUMINESCENCE ELEMENT AND ILLUMINATION DEVICE' [patent_app_type] => utility [patent_app_number] => 14/437517 [patent_app_country] => US [patent_app_date] => 2013-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 21131 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14437517 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/437517
ORGANIC ELECTROLUMINESCENCE ELEMENT AND ILLUMINATION DEVICE Oct 29, 2013 Abandoned
Array ( [id] => 10577156 [patent_doc_number] => 09299808 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-03-29 [patent_title] => 'Manufacturing method of low temperature polysilicon, low temperature polysilicon film and thin film transistor' [patent_app_type] => utility [patent_app_number] => 14/349583 [patent_app_country] => US [patent_app_date] => 2013-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 2967 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14349583 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/349583
Manufacturing method of low temperature polysilicon, low temperature polysilicon film and thin film transistor Oct 21, 2013 Issued
Array ( [id] => 9291336 [patent_doc_number] => 20140034970 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-02-06 [patent_title] => 'SEMICONDUCTOR STRUCTURES AND METHODS OF MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 14/052066 [patent_app_country] => US [patent_app_date] => 2013-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3752 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14052066 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/052066
Semiconductor structures and methods of manufacturing the same Oct 10, 2013 Issued
Array ( [id] => 14520131 [patent_doc_number] => 10337313 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-07-02 [patent_title] => Integrated well survey management and planning tool [patent_app_type] => utility [patent_app_number] => 15/021552 [patent_app_country] => US [patent_app_date] => 2013-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5141 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15021552 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/021552
Integrated well survey management and planning tool Oct 7, 2013 Issued
Array ( [id] => 9291400 [patent_doc_number] => 20140035034 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-02-06 [patent_title] => 'LATERAL-DIFFUSED METAL OXIDE SEMICONDUCTOR DEVICE (LDMOS) AND FABRICATION METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 14/044885 [patent_app_country] => US [patent_app_date] => 2013-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4509 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14044885 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/044885
Lateral-diffused metal oxide semiconductor device (LDMOS) and fabrication method thereof Oct 2, 2013 Issued
Array ( [id] => 9277961 [patent_doc_number] => 20140027929 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-01-30 [patent_title] => 'Semiconductor Device and Method of Forming Vertical Interconnect Structure with Conductive Micro Via Array for 3-D FO-WLCSP' [patent_app_type] => utility [patent_app_number] => 14/043751 [patent_app_country] => US [patent_app_date] => 2013-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 15420 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14043751 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/043751
Semiconductor device and method of forming vertical interconnect structure with conductive micro via array for 3-D Fo-WLCSP Sep 30, 2013 Issued
Array ( [id] => 9276681 [patent_doc_number] => 20140026649 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-01-30 [patent_title] => 'VERTICALLY INTEGRATED SYSTEMS' [patent_app_type] => utility [patent_app_number] => 14/041780 [patent_app_country] => US [patent_app_date] => 2013-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 42 [patent_figures_cnt] => 42 [patent_no_of_words] => 14558 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14041780 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/041780
Vertically integrated systems Sep 29, 2013 Issued
Array ( [id] => 9290470 [patent_doc_number] => 20140034104 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-02-06 [patent_title] => 'VERTICALLY INTEGRATED SYSTEMS' [patent_app_type] => utility [patent_app_number] => 14/041745 [patent_app_country] => US [patent_app_date] => 2013-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 42 [patent_figures_cnt] => 42 [patent_no_of_words] => 14530 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14041745 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/041745
Vertically integrated systems Sep 29, 2013 Issued
Array ( [id] => 9280897 [patent_doc_number] => 20140030865 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-01-30 [patent_title] => 'METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE HAVING CYLINDRICAL LOWER CAPACITOR ELECTRODE' [patent_app_type] => utility [patent_app_number] => 14/041475 [patent_app_country] => US [patent_app_date] => 2013-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 8677 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14041475 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/041475
METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE HAVING CYLINDRICAL LOWER CAPACITOR ELECTRODE Sep 29, 2013 Abandoned
Array ( [id] => 10864579 [patent_doc_number] => 08890285 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-11-18 [patent_title] => 'Vertically integrated systems' [patent_app_type] => utility [patent_app_number] => 14/041804 [patent_app_country] => US [patent_app_date] => 2013-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 41 [patent_figures_cnt] => 71 [patent_no_of_words] => 14558 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14041804 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/041804
Vertically integrated systems Sep 29, 2013 Issued
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