Search

Rocio Del Mar Perez-velez

Examiner (ID: 4591, Phone: (571)270-5935 , Office: P/2132 )

Most Active Art Unit
2132
Art Unit(s)
2182, 2100, 2187, 2117, 2133, 2132
Total Applications
254
Issued Applications
200
Pending Applications
5
Abandoned Applications
50

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 9778578 [patent_doc_number] => 08853786 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-10-07 [patent_title] => 'Semiconductor device with switching and rectifier cells' [patent_app_type] => utility [patent_app_number] => 13/933907 [patent_app_country] => US [patent_app_date] => 2013-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 13 [patent_no_of_words] => 6936 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13933907 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/933907
Semiconductor device with switching and rectifier cells Jul 1, 2013 Issued
Array ( [id] => 10016020 [patent_doc_number] => 09059041 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-06-16 [patent_title] => 'Dual channel hybrid semiconductor-on-insulator semiconductor devices' [patent_app_type] => utility [patent_app_number] => 13/933642 [patent_app_country] => US [patent_app_date] => 2013-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 6028 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13933642 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/933642
Dual channel hybrid semiconductor-on-insulator semiconductor devices Jul 1, 2013 Issued
Array ( [id] => 9796505 [patent_doc_number] => 20150008449 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-01-08 [patent_title] => 'METAL-OXIDE-SEMICONDUCTOR (MOS) DEVICES WITH INCREASED CHANNEL PERIPHERY AND METHODS OF MANUFACTURE' [patent_app_type] => utility [patent_app_number] => 13/934053 [patent_app_country] => US [patent_app_date] => 2013-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8126 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13934053 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/934053
Metal-oxide-semiconductor (MOS) devices with increased channel periphery and methods of manufacture Jul 1, 2013 Issued
Array ( [id] => 9789750 [patent_doc_number] => 20150001693 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-01-01 [patent_title] => 'LEADFRAME POCKET' [patent_app_type] => utility [patent_app_number] => 13/932756 [patent_app_country] => US [patent_app_date] => 2013-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2570 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13932756 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/932756
Leadframe pocket Jun 30, 2013 Issued
Array ( [id] => 9537748 [patent_doc_number] => 20140162395 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-06-12 [patent_title] => 'Method for Manufacturing Solar Cell' [patent_app_type] => utility [patent_app_number] => 13/932438 [patent_app_country] => US [patent_app_date] => 2013-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1693 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13932438 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/932438
Method for manufacturing solar cell Jun 30, 2013 Issued
Array ( [id] => 9676809 [patent_doc_number] => 08815718 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-08-26 [patent_title] => 'Vertical surround gate formation compatible with CMOS integration' [patent_app_type] => utility [patent_app_number] => 13/931803 [patent_app_country] => US [patent_app_date] => 2013-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 108 [patent_no_of_words] => 5495 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 209 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13931803 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/931803
Vertical surround gate formation compatible with CMOS integration Jun 27, 2013 Issued
Array ( [id] => 9792834 [patent_doc_number] => 20150004778 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-01-01 [patent_title] => 'HIGH LINEARITY SOI WAFER FOR LOW-DISTORTION CIRCUIT APPLICATIONS' [patent_app_type] => utility [patent_app_number] => 13/929955 [patent_app_country] => US [patent_app_date] => 2013-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3972 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13929955 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/929955
High linearity SOI wafer for low-distortion circuit applications Jun 27, 2013 Issued
Array ( [id] => 9792828 [patent_doc_number] => 20150004772 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-01-01 [patent_title] => 'FinFET Fin Bending Reduction' [patent_app_type] => utility [patent_app_number] => 13/930944 [patent_app_country] => US [patent_app_date] => 2013-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2273 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13930944 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/930944
FinFET fin bending reduction Jun 27, 2013 Issued
Array ( [id] => 9817640 [patent_doc_number] => 08927424 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-01-06 [patent_title] => 'Self-aligned patterning technique for semiconductor device features' [patent_app_type] => utility [patent_app_number] => 13/931798 [patent_app_country] => US [patent_app_date] => 2013-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 27 [patent_no_of_words] => 2763 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13931798 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/931798
Self-aligned patterning technique for semiconductor device features Jun 27, 2013 Issued
Array ( [id] => 9789668 [patent_doc_number] => 20150001612 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-01-01 [patent_title] => 'NON-VOLATILE MEMORY (NVM) AND HIGH VOLTAGE TRANSISTOR INTEGRATION' [patent_app_type] => utility [patent_app_number] => 13/928666 [patent_app_country] => US [patent_app_date] => 2013-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4595 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13928666 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/928666
Non-volatile memory (NVM) and high voltage transistor integration Jun 26, 2013 Issued
Array ( [id] => 13650229 [patent_doc_number] => 09851427 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-12-26 [patent_title] => Large-caliber telescope non-linear interference detecting and filtering method [patent_app_type] => utility [patent_app_number] => 14/426214 [patent_app_country] => US [patent_app_date] => 2013-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 12 [patent_no_of_words] => 3637 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 345 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14426214 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/426214
Large-caliber telescope non-linear interference detecting and filtering method Jun 24, 2013 Issued
Array ( [id] => 10974881 [patent_doc_number] => 20140377916 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-12-25 [patent_title] => 'METHODS TO PREVENT FILLER ENTRAPMENT IN MICROELECTRONIC DEVICE TO MICROELECTRONIC SUBSTRATE INTERCONNECTION STRUCTURES' [patent_app_type] => utility [patent_app_number] => 13/925967 [patent_app_country] => US [patent_app_date] => 2013-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4488 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13925967 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/925967
Methods to prevent filler entrapment in microelectronic device to microelectronic substrate interconnection structures Jun 24, 2013 Issued
Array ( [id] => 9575134 [patent_doc_number] => 08765546 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-07-01 [patent_title] => 'Method for fabricating fin-shaped field-effect transistor' [patent_app_type] => utility [patent_app_number] => 13/925812 [patent_app_country] => US [patent_app_date] => 2013-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 3413 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13925812 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/925812
Method for fabricating fin-shaped field-effect transistor Jun 23, 2013 Issued
Array ( [id] => 10858215 [patent_doc_number] => 08884419 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-11-11 [patent_title] => 'Integrated circuit packaging configurations' [patent_app_type] => utility [patent_app_number] => 13/924198 [patent_app_country] => US [patent_app_date] => 2013-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 13 [patent_no_of_words] => 7483 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13924198 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/924198
Integrated circuit packaging configurations Jun 20, 2013 Issued
Array ( [id] => 10898023 [patent_doc_number] => 08921236 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-12-30 [patent_title] => 'Patterning for selective area deposition' [patent_app_type] => utility [patent_app_number] => 13/923401 [patent_app_country] => US [patent_app_date] => 2013-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 36 [patent_no_of_words] => 13860 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13923401 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/923401
Patterning for selective area deposition Jun 20, 2013 Issued
Array ( [id] => 10974910 [patent_doc_number] => 20140377945 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-12-25 [patent_title] => 'FLOATING GATE FORMING PROCESS' [patent_app_type] => utility [patent_app_number] => 13/923374 [patent_app_country] => US [patent_app_date] => 2013-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2914 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13923374 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/923374
Floating gate forming process Jun 20, 2013 Issued
Array ( [id] => 10418389 [patent_doc_number] => 20150303399 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-10-22 [patent_title] => 'MASK PLATE, ORGANIC LIGHT-EMITTING DIODE (OLED) TRANSPARENT DISPLAY PANEL AND MANUFACTURING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 14/347079 [patent_app_country] => US [patent_app_date] => 2013-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4288 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14347079 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/347079
Mask plate, organic light-emitting diode (OLED) transparent display panel and manufacturing method thereof Jun 20, 2013 Issued
Array ( [id] => 10537902 [patent_doc_number] => 09263539 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-02-16 [patent_title] => 'Thin-film transistor and fabrication method thereof, array substrate and display device' [patent_app_type] => utility [patent_app_number] => 14/349120 [patent_app_country] => US [patent_app_date] => 2013-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 4 [patent_no_of_words] => 7949 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14349120 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/349120
Thin-film transistor and fabrication method thereof, array substrate and display device Jun 17, 2013 Issued
Array ( [id] => 10028763 [patent_doc_number] => 09070672 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-06-30 [patent_title] => 'Semiconductor device packaging structure and packaging method' [patent_app_type] => utility [patent_app_number] => 13/908246 [patent_app_country] => US [patent_app_date] => 2013-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 3258 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13908246 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/908246
Semiconductor device packaging structure and packaging method Jun 2, 2013 Issued
Array ( [id] => 9413451 [patent_doc_number] => 08697487 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-04-15 [patent_title] => 'Memory device manufacturing method with memory element having a metal-oxygen compound' [patent_app_type] => utility [patent_app_number] => 13/897109 [patent_app_country] => US [patent_app_date] => 2013-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 36 [patent_figures_cnt] => 46 [patent_no_of_words] => 8276 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13897109 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/897109
Memory device manufacturing method with memory element having a metal-oxygen compound May 16, 2013 Issued
Menu