
Rocio Del Mar Perez-velez
Examiner (ID: 4591, Phone: (571)270-5935 , Office: P/2132 )
| Most Active Art Unit | 2132 |
| Art Unit(s) | 2182, 2100, 2187, 2117, 2133, 2132 |
| Total Applications | 254 |
| Issued Applications | 200 |
| Pending Applications | 5 |
| Abandoned Applications | 50 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 9778578
[patent_doc_number] => 08853786
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2014-10-07
[patent_title] => 'Semiconductor device with switching and rectifier cells'
[patent_app_type] => utility
[patent_app_number] => 13/933907
[patent_app_country] => US
[patent_app_date] => 2013-07-02
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Array
(
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[patent_kind] => B2
[patent_issue_date] => 2015-06-16
[patent_title] => 'Dual channel hybrid semiconductor-on-insulator semiconductor devices'
[patent_app_type] => utility
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Array
(
[id] => 9796505
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[patent_kind] => A1
[patent_issue_date] => 2015-01-08
[patent_title] => 'METAL-OXIDE-SEMICONDUCTOR (MOS) DEVICES WITH INCREASED CHANNEL PERIPHERY AND METHODS OF MANUFACTURE'
[patent_app_type] => utility
[patent_app_number] => 13/934053
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/934053 | Metal-oxide-semiconductor (MOS) devices with increased channel periphery and methods of manufacture | Jul 1, 2013 | Issued |
Array
(
[id] => 9789750
[patent_doc_number] => 20150001693
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[patent_kind] => A1
[patent_issue_date] => 2015-01-01
[patent_title] => 'LEADFRAME POCKET'
[patent_app_type] => utility
[patent_app_number] => 13/932756
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Array
(
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[patent_doc_number] => 20140162395
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[patent_issue_date] => 2014-06-12
[patent_title] => 'Method for Manufacturing Solar Cell'
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Array
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[patent_title] => 'Vertical surround gate formation compatible with CMOS integration'
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Array
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[patent_title] => 'HIGH LINEARITY SOI WAFER FOR LOW-DISTORTION CIRCUIT APPLICATIONS'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/929955 | High linearity SOI wafer for low-distortion circuit applications | Jun 27, 2013 | Issued |
Array
(
[id] => 9792828
[patent_doc_number] => 20150004772
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[patent_issue_date] => 2015-01-01
[patent_title] => 'FinFET Fin Bending Reduction'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/930944 | FinFET fin bending reduction | Jun 27, 2013 | Issued |
Array
(
[id] => 9817640
[patent_doc_number] => 08927424
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[patent_issue_date] => 2015-01-06
[patent_title] => 'Self-aligned patterning technique for semiconductor device features'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/931798 | Self-aligned patterning technique for semiconductor device features | Jun 27, 2013 | Issued |
Array
(
[id] => 9789668
[patent_doc_number] => 20150001612
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[patent_issue_date] => 2015-01-01
[patent_title] => 'NON-VOLATILE MEMORY (NVM) AND HIGH VOLTAGE TRANSISTOR INTEGRATION'
[patent_app_type] => utility
[patent_app_number] => 13/928666
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/928666 | Non-volatile memory (NVM) and high voltage transistor integration | Jun 26, 2013 | Issued |
Array
(
[id] => 13650229
[patent_doc_number] => 09851427
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[patent_title] => Large-caliber telescope non-linear interference detecting and filtering method
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[rel_patent_id] =>[rel_patent_doc_number] =>) 14/426214 | Large-caliber telescope non-linear interference detecting and filtering method | Jun 24, 2013 | Issued |
Array
(
[id] => 10974881
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[patent_title] => 'METHODS TO PREVENT FILLER ENTRAPMENT IN MICROELECTRONIC DEVICE TO MICROELECTRONIC SUBSTRATE INTERCONNECTION STRUCTURES'
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Array
(
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[patent_title] => 'Method for fabricating fin-shaped field-effect transistor'
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Array
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Array
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Array
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