
Rocio Del Mar Perez-velez
Examiner (ID: 4591, Phone: (571)270-5935 , Office: P/2132 )
| Most Active Art Unit | 2132 |
| Art Unit(s) | 2182, 2100, 2187, 2117, 2133, 2132 |
| Total Applications | 254 |
| Issued Applications | 200 |
| Pending Applications | 5 |
| Abandoned Applications | 50 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 9691743
[patent_doc_number] => 08822337
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2014-09-02
[patent_title] => 'Two-sided semiconductor structure'
[patent_app_type] => utility
[patent_app_number] => 13/607676
[patent_app_country] => US
[patent_app_date] => 2012-09-08
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Array
(
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[patent_doc_number] => 20160013417
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[patent_kind] => A1
[patent_issue_date] => 2016-01-14
[patent_title] => 'ORGANIC ELECTROLUMINESCENCE DEVICE AND MANUFACTURING METHOD THEREOF'
[patent_app_type] => utility
[patent_app_number] => 14/425280
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[rel_patent_id] =>[rel_patent_doc_number] =>) 14/425280 | Organic electroluminescence device and manufacturing method thereof | Sep 6, 2012 | Issued |
Array
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[patent_kind] => B2
[patent_issue_date] => 2014-09-23
[patent_title] => 'Bulk finFET with controlled fin height and high-K liner'
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Array
(
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[patent_kind] => A1
[patent_issue_date] => 2013-07-04
[patent_title] => 'SEMICONDUCTOR DEVICES HAVING NITRIDED GATE INSULATING LAYER AND METHODS OF FABRICATING THE SAME'
[patent_app_type] => utility
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Array
(
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[patent_title] => 'ELECTRO-OPTICAL DEVICE AND ELECTRONIC APPARATUS'
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Array
(
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[patent_issue_date] => 2012-12-27
[patent_title] => 'METHODS OF FORMING SEMICONDUCTOR DEVICES HAVING DIFFUSION REGIONS OF REDUCED WIDTH'
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Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/602388 | MANUFACTURING A FILLING OF A GAP REGION | Sep 3, 2012 | Abandoned |
Array
(
[id] => 8519700
[patent_doc_number] => 20120319108
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[patent_kind] => A1
[patent_issue_date] => 2012-12-20
[patent_title] => 'TRANSISTOR, SEMICONDUCTOR DEVICE INCLUDING THE TRANSISTOR, AND MANUFACTURING METHOD OF THE TRANSISTOR AND THE SEMICONDUCTOR DEVICE'
[patent_app_type] => utility
[patent_app_number] => 13/602393
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/602393 | Transistor, semiconductor device including the transistor, and manufacturing method of the transistor and the semiconductor device | Sep 3, 2012 | Issued |
Array
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[id] => 9339050
[patent_doc_number] => 20140065832
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-03-06
[patent_title] => 'ENHANCED FINFET PROCESS OVERLAY MARK'
[patent_app_type] => utility
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/602697 | Enhanced FinFET process overlay mark | Sep 3, 2012 | Issued |
Array
(
[id] => 9649304
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[patent_issue_date] => 2014-08-12
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Array
(
[id] => 9552136
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[patent_issue_date] => 2014-06-24
[patent_title] => 'Methods of forming semiconductor devices using electrolyzed sulfuric acid (ESA)'
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Array
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[patent_title] => 'DOPING OF COPPER WIRING STRUCTURES IN BACK END OF LINE PROCESSING'
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Array
(
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Array
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Array
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Array
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