Search

Rocio Del Mar Perez-velez

Examiner (ID: 4591, Phone: (571)270-5935 , Office: P/2132 )

Most Active Art Unit
2132
Art Unit(s)
2182, 2100, 2187, 2117, 2133, 2132
Total Applications
254
Issued Applications
200
Pending Applications
5
Abandoned Applications
50

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 8310549 [patent_doc_number] => 20120187568 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-07-26 [patent_title] => 'Semiconductor Device and Method of Forming FO-WLCSP with Multiple Encapsulants' [patent_app_type] => utility [patent_app_number] => 13/326157 [patent_app_country] => US [patent_app_date] => 2011-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 13287 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13326157 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/326157
Semiconductor device and method of forming FO-WLCSP with multiple encapsulants Dec 13, 2011 Issued
Array ( [id] => 8880924 [patent_doc_number] => 20130154108 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-06-20 [patent_title] => 'Semiconductor Device and Method of Forming Vertical Interconnect Structure with Conductive Micro Via Array for 3-D FO-WLCSP' [patent_app_type] => utility [patent_app_number] => 13/326128 [patent_app_country] => US [patent_app_date] => 2011-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 15414 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13326128 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/326128
Semiconductor device and method of forming vertical interconnect structure with conductive micro via array for 3-D Fo-WLCSP Dec 13, 2011 Issued
Array ( [id] => 9086812 [patent_doc_number] => 08558242 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-10-15 [patent_title] => 'Vertical GaN-based metal insulator semiconductor FET' [patent_app_type] => utility [patent_app_number] => 13/315705 [patent_app_country] => US [patent_app_date] => 2011-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 18 [patent_no_of_words] => 6052 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13315705 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/315705
Vertical GaN-based metal insulator semiconductor FET Dec 8, 2011 Issued
Array ( [id] => 9869650 [patent_doc_number] => 08957425 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-02-17 [patent_title] => 'Semiconductor device and method for manufacturing semiconductor device' [patent_app_type] => utility [patent_app_number] => 13/315682 [patent_app_country] => US [patent_app_date] => 2011-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 15 [patent_no_of_words] => 3597 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13315682 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/315682
Semiconductor device and method for manufacturing semiconductor device Dec 8, 2011 Issued
Array ( [id] => 9414127 [patent_doc_number] => 08698164 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-04-15 [patent_title] => 'Vertical GaN JFET with gate source electrodes on regrown gate' [patent_app_type] => utility [patent_app_number] => 13/315720 [patent_app_country] => US [patent_app_date] => 2011-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 6465 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13315720 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/315720
Vertical GaN JFET with gate source electrodes on regrown gate Dec 8, 2011 Issued
Array ( [id] => 9869650 [patent_doc_number] => 08957425 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-02-17 [patent_title] => 'Semiconductor device and method for manufacturing semiconductor device' [patent_app_type] => utility [patent_app_number] => 13/315682 [patent_app_country] => US [patent_app_date] => 2011-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 15 [patent_no_of_words] => 3597 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13315682 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/315682
Semiconductor device and method for manufacturing semiconductor device Dec 8, 2011 Issued
Array ( [id] => 9869650 [patent_doc_number] => 08957425 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-02-17 [patent_title] => 'Semiconductor device and method for manufacturing semiconductor device' [patent_app_type] => utility [patent_app_number] => 13/315682 [patent_app_country] => US [patent_app_date] => 2011-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 15 [patent_no_of_words] => 3597 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13315682 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/315682
Semiconductor device and method for manufacturing semiconductor device Dec 8, 2011 Issued
Array ( [id] => 9869650 [patent_doc_number] => 08957425 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-02-17 [patent_title] => 'Semiconductor device and method for manufacturing semiconductor device' [patent_app_type] => utility [patent_app_number] => 13/315682 [patent_app_country] => US [patent_app_date] => 2011-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 15 [patent_no_of_words] => 3597 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13315682 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/315682
Semiconductor device and method for manufacturing semiconductor device Dec 8, 2011 Issued
Array ( [id] => 9086234 [patent_doc_number] => 08557661 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-10-15 [patent_title] => 'Methods of manufacturing a semiconductor device and a semiconductor memory device thereby' [patent_app_type] => utility [patent_app_number] => 13/314627 [patent_app_country] => US [patent_app_date] => 2011-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 38 [patent_no_of_words] => 9373 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13314627 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/314627
Methods of manufacturing a semiconductor device and a semiconductor memory device thereby Dec 7, 2011 Issued
Array ( [id] => 8299018 [patent_doc_number] => 20120181577 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-07-19 [patent_title] => 'SEMICONDUCTOR WAFER AND SEMICONDUCTOR DEVICE HAVING MULTILAYERED NITRIDE SEMICONDUCTOR LAYER' [patent_app_type] => utility [patent_app_number] => 13/314466 [patent_app_country] => US [patent_app_date] => 2011-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5357 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13314466 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/314466
Semiconductor wafer and semiconductor device having multilayered nitride semiconductor layer Dec 7, 2011 Issued
Array ( [id] => 8863343 [patent_doc_number] => 20130147046 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-06-13 [patent_title] => 'Integrated Technology for Partial Air Gap Low K Deposition' [patent_app_type] => utility [patent_app_number] => 13/313542 [patent_app_country] => US [patent_app_date] => 2011-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3518 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13313542 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/313542
Integrated technology for partial air gap low K deposition Dec 6, 2011 Issued
Array ( [id] => 8224904 [patent_doc_number] => 20120139110 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-06-07 [patent_title] => 'TAPE' [patent_app_type] => utility [patent_app_number] => 13/313453 [patent_app_country] => US [patent_app_date] => 2011-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3819 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13313453 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/313453
TAPE Dec 6, 2011 Abandoned
Array ( [id] => 8851016 [patent_doc_number] => 20130140691 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-06-06 [patent_title] => 'Semiconductor Device and Method of Forming Patterned Repassivation Openings Between RDL and UBM to Reduce Adverse Effects of Electro-Migration' [patent_app_type] => utility [patent_app_number] => 13/312730 [patent_app_country] => US [patent_app_date] => 2011-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5457 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13312730 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/312730
Semiconductor device and method of forming patterned repassivation openings between RDL and UBM to reduce adverse effects of electro-migration Dec 5, 2011 Issued
Array ( [id] => 8753529 [patent_doc_number] => 20130087833 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-04-11 [patent_title] => 'SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 13/582433 [patent_app_country] => US [patent_app_date] => 2011-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5286 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13582433 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/582433
Semiconductor device and method of manufacturing the same Nov 29, 2011 Issued
Array ( [id] => 10038572 [patent_doc_number] => 09079269 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-07-14 [patent_title] => 'Spalling with laser-defined spall edge regions' [patent_app_type] => utility [patent_app_number] => 13/302427 [patent_app_country] => US [patent_app_date] => 2011-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 22 [patent_no_of_words] => 8831 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13302427 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/302427
Spalling with laser-defined spall edge regions Nov 21, 2011 Issued
Array ( [id] => 7815150 [patent_doc_number] => 20120061770 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-03-15 [patent_title] => 'Nonvolatile Memory Device and Method of Manufacturing the Same' [patent_app_type] => utility [patent_app_number] => 13/298096 [patent_app_country] => US [patent_app_date] => 2011-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 12035 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0061/20120061770.pdf [firstpage_image] =>[orig_patent_app_number] => 13298096 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/298096
Nonvolatile Memory Device and Method of Manufacturing the Same Nov 15, 2011 Abandoned
Array ( [id] => 9350676 [patent_doc_number] => 08669569 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-03-11 [patent_title] => 'Light emitting diode package and method for fabricating the same' [patent_app_type] => utility [patent_app_number] => 13/251442 [patent_app_country] => US [patent_app_date] => 2011-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 12 [patent_no_of_words] => 3515 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13251442 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/251442
Light emitting diode package and method for fabricating the same Oct 2, 2011 Issued
Array ( [id] => 9047239 [patent_doc_number] => 08541793 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-09-24 [patent_title] => 'Light emitting diode device and method for fabricating the same' [patent_app_type] => utility [patent_app_number] => 13/251460 [patent_app_country] => US [patent_app_date] => 2011-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 18 [patent_no_of_words] => 3945 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 212 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13251460 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/251460
Light emitting diode device and method for fabricating the same Oct 2, 2011 Issued
Array ( [id] => 8920827 [patent_doc_number] => 08486759 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-07-16 [patent_title] => 'Method for forming terminal of stacked package element and method for forming stacked package' [patent_app_type] => utility [patent_app_number] => 13/241724 [patent_app_country] => US [patent_app_date] => 2011-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 6888 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13241724 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/241724
Method for forming terminal of stacked package element and method for forming stacked package Sep 22, 2011 Issued
Array ( [id] => 8870630 [patent_doc_number] => 08466007 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-06-18 [patent_title] => 'Power semiconductor module and fabrication method' [patent_app_type] => utility [patent_app_number] => 13/236748 [patent_app_country] => US [patent_app_date] => 2011-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 50 [patent_no_of_words] => 5145 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13236748 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/236748
Power semiconductor module and fabrication method Sep 19, 2011 Issued
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