
Rocio Del Mar Perez-velez
Examiner (ID: 4591, Phone: (571)270-5935 , Office: P/2132 )
| Most Active Art Unit | 2132 |
| Art Unit(s) | 2182, 2100, 2187, 2117, 2133, 2132 |
| Total Applications | 254 |
| Issued Applications | 200 |
| Pending Applications | 5 |
| Abandoned Applications | 50 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 7558902
[patent_doc_number] => 20110272733
[patent_country] => US
[patent_kind] => A1
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[patent_title] => 'ENCAPSULATION STRUCTURE FOR LIGHT-EMITTING DIODE'
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[pdf_file] => publications/A1/0272/20110272733.pdf
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/776037 | ENCAPSULATION STRUCTURE FOR LIGHT-EMITTING DIODE | May 6, 2010 | Abandoned |
Array
(
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[patent_issue_date] => 2013-03-26
[patent_title] => 'Organic semiconductor polymer and transistor including the same'
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Array
(
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[patent_issue_date] => 2011-11-10
[patent_title] => 'ORGANIC THIN FILM DEVICES WITH STABILIZED THRESHOLD VOLTAGE AND MOBILITY, AND METHOD FOR PREPARING THE DEVICES'
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Array
(
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[patent_issue_date] => 2010-11-11
[patent_title] => 'METAL OPTICAL FILTER CAPABLE OF PHOTO LITHOGRAPHY PROCESS AND IMAGE SENSOR INCLUDING THE SAME'
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Array
(
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[patent_title] => 'Semiconductor device packaging structure and packaging method'
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Array
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Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/774320 | Electronic device | May 4, 2010 | Issued |
Array
(
[id] => 6256354
[patent_doc_number] => 20100295185
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[patent_issue_date] => 2010-11-25
[patent_title] => 'Nonvolatile Memory Device and Method of Manufacturing the Same'
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Array
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[id] => 6375680
[patent_doc_number] => 20100301421
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[patent_issue_date] => 2010-12-02
[patent_title] => 'STRAIN ENHANCEMENT IN TRANSISTORS COMPRISING AN EMBEDDED STRAIN-INDUCING SEMICONDUCTOR ALLOY BY CREATING A PATTERNING NON-UNIFORMITY AT THE BOTTOM OF THE GATE ELECTRODE'
[patent_app_type] => utility
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/772436 | Strain enhancement in transistors comprising an embedded strain-inducing semiconductor alloy by creating a patterning non-uniformity at the bottom of the gate electrode | May 2, 2010 | Issued |
Array
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[id] => 6137358
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[patent_issue_date] => 2011-06-02
[patent_title] => 'Lateral super junction device with high substrate-gate breakdown and built-in avalanche clamp diode'
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[patent_app_number] => 12/799810
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Array
(
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[patent_title] => 'IN-SITU DEFECT REDUCTION TECHNIQUES FOR NONPOLAR AND SEMIPOLAR (Al, Ga, In)N'
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Array
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Array
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Array
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Array
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Array
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Array
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