
Rocio Del Mar Perez-velez
Examiner (ID: 4591, Phone: (571)270-5935 , Office: P/2132 )
| Most Active Art Unit | 2132 |
| Art Unit(s) | 2182, 2100, 2187, 2117, 2133, 2132 |
| Total Applications | 254 |
| Issued Applications | 200 |
| Pending Applications | 5 |
| Abandoned Applications | 50 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 4816931
[patent_doc_number] => 20080224190
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-09-18
[patent_title] => 'IMAGE SENSOR AND METHOD OF FABRICATING THE SAME'
[patent_app_type] => utility
[patent_app_number] => 12/046965
[patent_app_country] => US
[patent_app_date] => 2008-03-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
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[patent_no_of_words] => 8780
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[pdf_file] => publications/A1/0224/20080224190.pdf
[firstpage_image] =>[orig_patent_app_number] => 12046965
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/046965 | IMAGE SENSOR AND METHOD OF FABRICATING THE SAME | Mar 11, 2008 | Abandoned |
Array
(
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[patent_doc_number] => 07615411
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-11-10
[patent_title] => 'Semiconductor package including connected upper and lower interconnections, and manufacturing method thereof'
[patent_app_type] => utility
[patent_app_number] => 12/047228
[patent_app_country] => US
[patent_app_date] => 2008-03-12
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[pdf_file] => patents/07/615/07615411.pdf
[firstpage_image] =>[orig_patent_app_number] => 12047228
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/047228 | Semiconductor package including connected upper and lower interconnections, and manufacturing method thereof | Mar 11, 2008 | Issued |
Array
(
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[patent_kind] => B2
[patent_issue_date] => 2010-04-13
[patent_title] => 'Structure for a latchup robust gate array using through wafer via'
[patent_app_type] => utility
[patent_app_number] => 12/043212
[patent_app_country] => US
[patent_app_date] => 2008-03-06
[patent_effective_date] => 0000-00-00
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[firstpage_image] =>[orig_patent_app_number] => 12043212
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/043212 | Structure for a latchup robust gate array using through wafer via | Mar 5, 2008 | Issued |
Array
(
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[patent_doc_number] => 20080211016
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[patent_kind] => A1
[patent_issue_date] => 2008-09-04
[patent_title] => 'TRENCH MOSGATED DEVICE WITH DEEP TRENCH BETWEEN GATE TRENCHES'
[patent_app_type] => utility
[patent_app_number] => 12/041017
[patent_app_country] => US
[patent_app_date] => 2008-03-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/041017 | Trench MOSgated device with deep trench between gate trenches | Mar 2, 2008 | Issued |
Array
(
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[patent_title] => 'Stress-modified device structures, methods of fabricating such stress-modified device structures, and design structures for an integrated circuit'
[patent_app_type] => utility
[patent_app_number] => 12/030917
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[pdf_file] => patents/07/843/07843039.pdf
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/030917 | Stress-modified device structures, methods of fabricating such stress-modified device structures, and design structures for an integrated circuit | Feb 13, 2008 | Issued |
Array
(
[id] => 8533686
[patent_doc_number] => 08309842
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[patent_issue_date] => 2012-11-13
[patent_title] => 'Method and device of diamond like carbon multi-layer doping growth'
[patent_app_type] => utility
[patent_app_number] => 12/525918
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Array
(
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[patent_title] => 'Multiple patterning using patternable low-k dielectric materials'
[patent_app_type] => utility
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Array
(
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[patent_doc_number] => 07755145
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[patent_title] => 'Semiconductor device and manufacturing method thereof'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/028258 | Semiconductor device and manufacturing method thereof | Feb 7, 2008 | Issued |
Array
(
[id] => 5524800
[patent_doc_number] => 20090194876
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[patent_issue_date] => 2009-08-06
[patent_title] => 'INTERCONNECT STRUCTURE AND METHOD FOR Cu/ULTRA LOW k INTEGRATION'
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[patent_app_number] => 12/025297
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/025297 | Interconnect structure and method for Cu/ultra low k integration | Feb 3, 2008 | Issued |
Array
(
[id] => 4952574
[patent_doc_number] => 20080185598
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[patent_issue_date] => 2008-08-07
[patent_title] => 'LIGHT EMITTING DEVICE'
[patent_app_type] => utility
[patent_app_number] => 12/024378
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/024378 | LIGHT EMITTING DEVICE | Jan 31, 2008 | Abandoned |
Array
(
[id] => 4673383
[patent_doc_number] => 20080211011
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[patent_title] => 'NONVOLATILE SEMICONDUCTOR MEMORY ELEMENT AND NONVOLATILE SEMICONDUCTOR MEMORY DEVICE'
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Array
(
[id] => 4435205
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Array
(
[id] => 4842046
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[patent_title] => 'Electronic Textiles with Electronic Devices on Ribbons'
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Array
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Array
(
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Array
(
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[patent_title] => 'METHOD FOR NON-SELECTIVE SHALLOW TRENCH ISOLATION REACTIVE ION ETCH FOR PATTERNING HYBRID-ORIENTED DEVICES COMPATIBLE WITH HIGH-PERFORMANCE HIGHLY-INTEGRATED LOGIC DEVICES'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/020887 | Method for non-selective shallow trench isolation reactive ion etch for patterning hybrid-oriented devices compatible with high-performance highly-integrated logic devices | Jan 27, 2008 | Issued |
Array
(
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Array
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Array
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Array
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