
Rocio Del Mar Perez-velez
Examiner (ID: 4591, Phone: (571)270-5935 , Office: P/2132 )
| Most Active Art Unit | 2132 |
| Art Unit(s) | 2182, 2100, 2187, 2117, 2133, 2132 |
| Total Applications | 254 |
| Issued Applications | 200 |
| Pending Applications | 5 |
| Abandoned Applications | 50 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 18789464
[patent_doc_number] => 20230378134
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-11-23
[patent_title] => STACKED INTEGRATED CIRCUIT
[patent_app_type] => utility
[patent_app_number] => 17/893806
[patent_app_country] => US
[patent_app_date] => 2022-08-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 17254
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -51
[patent_words_short_claim] => 83
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17893806
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/893806 | STACKED INTEGRATED CIRCUIT | Aug 22, 2022 | Pending |
Array
(
[id] => 18789464
[patent_doc_number] => 20230378134
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-11-23
[patent_title] => STACKED INTEGRATED CIRCUIT
[patent_app_type] => utility
[patent_app_number] => 17/893806
[patent_app_country] => US
[patent_app_date] => 2022-08-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 17254
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -51
[patent_words_short_claim] => 83
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17893806
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/893806 | STACKED INTEGRATED CIRCUIT | Aug 22, 2022 | Pending |
Array
(
[id] => 19007397
[patent_doc_number] => 20240071468
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-02-29
[patent_title] => WORD LINE DRIVERS FOR MULTIPLE-DIE MEMORY DEVICES
[patent_app_type] => utility
[patent_app_number] => 17/893672
[patent_app_country] => US
[patent_app_date] => 2022-08-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 17107
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -22
[patent_words_short_claim] => 110
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17893672
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/893672 | Word line drivers for multiple-die memory devices | Aug 22, 2022 | Issued |
Array
(
[id] => 18991183
[patent_doc_number] => 20240063152
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-02-22
[patent_title] => HYBRID BONDING FOR SEMICONDUCTOR DEVICE ASSEMBLIES
[patent_app_type] => utility
[patent_app_number] => 17/893160
[patent_app_country] => US
[patent_app_date] => 2022-08-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6798
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 136
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17893160
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/893160 | HYBRID BONDING FOR SEMICONDUCTOR DEVICE ASSEMBLIES | Aug 21, 2022 | Pending |
Array
(
[id] => 20346073
[patent_doc_number] => 12469808
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-11-11
[patent_title] => Semiconductor package and manufacturing method thereof
[patent_app_type] => utility
[patent_app_number] => 17/892102
[patent_app_country] => US
[patent_app_date] => 2022-08-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 20
[patent_figures_cnt] => 20
[patent_no_of_words] => 1969
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 81
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17892102
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/892102 | Semiconductor package and manufacturing method thereof | Aug 20, 2022 | Issued |
Array
(
[id] => 20360228
[patent_doc_number] => 12476234
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-11-18
[patent_title] => Semiconductor device including through electrodes
[patent_app_type] => utility
[patent_app_number] => 17/891629
[patent_app_country] => US
[patent_app_date] => 2022-08-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 16
[patent_no_of_words] => 3443
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 200
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17891629
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/891629 | Semiconductor device including through electrodes | Aug 18, 2022 | Issued |
Array
(
[id] => 18991163
[patent_doc_number] => 20240063132
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-02-22
[patent_title] => PACKAGE ARCHITECTURE OF LARGE DIES USING QUASI-MONOLITHIC CHIP LAYERS
[patent_app_type] => utility
[patent_app_number] => 17/820993
[patent_app_country] => US
[patent_app_date] => 2022-08-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 16581
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 147
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17820993
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/820993 | PACKAGE ARCHITECTURE OF LARGE DIES USING QUASI-MONOLITHIC CHIP LAYERS | Aug 18, 2022 | Pending |
Array
(
[id] => 19428329
[patent_doc_number] => 12087764
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-09-10
[patent_title] => Device integration schemes leveraging a bulk semiconductor substrate having a <111> crystal orientation
[patent_app_type] => utility
[patent_app_number] => 17/890446
[patent_app_country] => US
[patent_app_date] => 2022-08-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 11
[patent_no_of_words] => 4545
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 99
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17890446
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/890446 | Device integration schemes leveraging a bulk semiconductor substrate having a <111> crystal orientation | Aug 17, 2022 | Issued |
Array
(
[id] => 18959090
[patent_doc_number] => 20240047417
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-02-08
[patent_title] => Integrated Circuit Package and Method of Forming the Same
[patent_app_type] => utility
[patent_app_number] => 17/817738
[patent_app_country] => US
[patent_app_date] => 2022-08-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 13806
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 119
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17817738
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/817738 | Integrated circuit package and method of forming the same | Aug 4, 2022 | Issued |
Array
(
[id] => 18891044
[patent_doc_number] => 11869821
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-01-09
[patent_title] => Semiconductor package having molding layer with inclined side wall
[patent_app_type] => utility
[patent_app_number] => 17/879272
[patent_app_country] => US
[patent_app_date] => 2022-08-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 32
[patent_figures_cnt] => 32
[patent_no_of_words] => 14586
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 158
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17879272
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/879272 | Semiconductor package having molding layer with inclined side wall | Aug 1, 2022 | Issued |
Array
(
[id] => 18040157
[patent_doc_number] => 20220384374
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-12-01
[patent_title] => Chiplets 3D SoIC System Integration and Fabrication Methods
[patent_app_type] => utility
[patent_app_number] => 17/815738
[patent_app_country] => US
[patent_app_date] => 2022-07-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7303
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 120
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17815738
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/815738 | Chiplets 3D SoIC system integration and fabrication methods | Jul 27, 2022 | Issued |
Array
(
[id] => 18927205
[patent_doc_number] => 20240030209
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-01-25
[patent_title] => PARTITIONED OVERLAPPED COPPER-BONDED INTERPOSERS
[patent_app_type] => utility
[patent_app_number] => 17/872371
[patent_app_country] => US
[patent_app_date] => 2022-07-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4055
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 48
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17872371
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/872371 | PARTITIONED OVERLAPPED COPPER-BONDED INTERPOSERS | Jul 24, 2022 | Pending |
Array
(
[id] => 18221734
[patent_doc_number] => 20230060728
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-03-02
[patent_title] => SOC PMUT SUITABLE FOR HIGH-DENSITY SYSTEM INTEGRATION, ARRAY CHIP, AND MANUFACTURING METHOD THEREOF
[patent_app_type] => utility
[patent_app_number] => 17/870810
[patent_app_country] => US
[patent_app_date] => 2022-07-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 11146
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -11
[patent_words_short_claim] => 341
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17870810
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/870810 | SOC PMUT suitable for high-density system integration, array chip, and manufacturing method thereof | Jul 20, 2022 | Issued |
Array
(
[id] => 17993521
[patent_doc_number] => 20220359558
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-11-10
[patent_title] => BOUNDARY DESIGN TO REDUCE MEMORY ARRAY EDGE CMP DISHING EFFECT
[patent_app_type] => utility
[patent_app_number] => 17/866922
[patent_app_country] => US
[patent_app_date] => 2022-07-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 11511
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 74
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17866922
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/866922 | Boundary design to reduce memory array edge CMP dishing effect | Jul 17, 2022 | Issued |
Array
(
[id] => 18639569
[patent_doc_number] => 11764192
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-09-19
[patent_title] => Semiconductor package including underfill material layer and method of forming the same
[patent_app_type] => utility
[patent_app_number] => 17/861580
[patent_app_country] => US
[patent_app_date] => 2022-07-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 29
[patent_figures_cnt] => 29
[patent_no_of_words] => 14093
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 107
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17861580
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/861580 | Semiconductor package including underfill material layer and method of forming the same | Jul 10, 2022 | Issued |
Array
(
[id] => 20246130
[patent_doc_number] => 12426476
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-09-23
[patent_title] => Display panel and display device
[patent_app_type] => utility
[patent_app_number] => 17/856592
[patent_app_country] => US
[patent_app_date] => 2022-07-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 0
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 121
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17856592
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/856592 | Display panel and display device | Jun 30, 2022 | Issued |
Array
(
[id] => 19046733
[patent_doc_number] => 11935853
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-03-19
[patent_title] => Memory devices with backside bond pads under a memory array
[patent_app_type] => utility
[patent_app_number] => 17/854428
[patent_app_country] => US
[patent_app_date] => 2022-06-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 19
[patent_no_of_words] => 4300
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 124
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17854428
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/854428 | Memory devices with backside bond pads under a memory array | Jun 29, 2022 | Issued |
Array
(
[id] => 18309565
[patent_doc_number] => 20230113465
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-04-13
[patent_title] => SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME
[patent_app_type] => utility
[patent_app_number] => 17/854659
[patent_app_country] => US
[patent_app_date] => 2022-06-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9256
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17854659
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/854659 | Semiconductor package with bonding interface | Jun 29, 2022 | Issued |
Array
(
[id] => 18866063
[patent_doc_number] => 20230420500
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-12-28
[patent_title] => CPP-AGNOSTIC SOURCE-DRAIN CONTACT FORMATION FOR GATE-ALL-AROUND DEVICES WITH DIELECTRIC ISOLATION
[patent_app_type] => utility
[patent_app_number] => 17/850475
[patent_app_country] => US
[patent_app_date] => 2022-06-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10319
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 152
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17850475
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/850475 | CPP-agnostic source-drain contact formation for gate-all-around devices with dielectric isolation | Jun 26, 2022 | Issued |
Array
(
[id] => 18866063
[patent_doc_number] => 20230420500
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-12-28
[patent_title] => CPP-AGNOSTIC SOURCE-DRAIN CONTACT FORMATION FOR GATE-ALL-AROUND DEVICES WITH DIELECTRIC ISOLATION
[patent_app_type] => utility
[patent_app_number] => 17/850475
[patent_app_country] => US
[patent_app_date] => 2022-06-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10319
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 152
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17850475
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/850475 | CPP-agnostic source-drain contact formation for gate-all-around devices with dielectric isolation | Jun 26, 2022 | Issued |