Search

Rodney T. Frank

Examiner (ID: 9476)

Most Active Art Unit
2856
Art Unit(s)
2861, 2856, 2855
Total Applications
1677
Issued Applications
1243
Pending Applications
133
Abandoned Applications
327

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 20667374 [patent_doc_number] => 12609154 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-04-21 [patent_title] => Data buffer circuit structure, layout structure of multiple data buffer circuits, and memory [patent_app_type] => utility [patent_app_number] => 18/820305 [patent_app_country] => US [patent_app_date] => 2024-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 2266 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18820305 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/820305
Data buffer circuit structure, layout structure of multiple data buffer circuits, and memory Aug 29, 2024 Issued
Array ( [id] => 19604438 [patent_doc_number] => 20240395318 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-28 [patent_title] => MEMORY DEVICE INCLUDING BOOSTER CIRCUIT FOR TRACKING WORD LINE [patent_app_type] => utility [patent_app_number] => 18/790373 [patent_app_country] => US [patent_app_date] => 2024-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14083 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18790373 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/790373
MEMORY DEVICE INCLUDING BOOSTER CIRCUIT FOR TRACKING WORD LINE Jul 30, 2024 Pending
Array ( [id] => 19591797 [patent_doc_number] => 20240389354 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-21 [patent_title] => CIRCUIT AND METHOD TO ENHANCE EFFICIENCY OF MEMORY [patent_app_type] => utility [patent_app_number] => 18/786588 [patent_app_country] => US [patent_app_date] => 2024-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6410 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18786588 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/786588
CIRCUIT AND METHOD TO ENHANCE EFFICIENCY OF MEMORY Jul 28, 2024 Pending
Array ( [id] => 20324347 [patent_doc_number] => 20250336435 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-10-30 [patent_title] => MEMORY DEVICE AND MANUFACTURING METHOD THEREOF, AND MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 18/781547 [patent_app_country] => US [patent_app_date] => 2024-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6240 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18781547 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/781547
MEMORY DEVICE AND MANUFACTURING METHOD THEREOF, AND MEMORY SYSTEM Jul 22, 2024 Pending
Array ( [id] => 19574880 [patent_doc_number] => 20240379172 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-14 [patent_title] => READING OF SOFT BITS AND HARD BITS FROM MEMORY CELLS [patent_app_type] => utility [patent_app_number] => 18/778823 [patent_app_country] => US [patent_app_date] => 2024-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11897 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18778823 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/778823
READING OF SOFT BITS AND HARD BITS FROM MEMORY CELLS Jul 18, 2024 Pending
Array ( [id] => 20690271 [patent_doc_number] => 12620428 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-05-05 [patent_title] => Selector only memory write operation [patent_app_type] => utility [patent_app_number] => 18/757102 [patent_app_country] => US [patent_app_date] => 2024-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 19 [patent_no_of_words] => 11430 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 216 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18757102 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/757102
SELECTOR ONLY MEMORY WRITE OPERATION Jun 26, 2024 Issued
Array ( [id] => 20448119 [patent_doc_number] => 20260004843 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-01-01 [patent_title] => SEMICONDUCTOR DEVICE AND OPERATING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/756142 [patent_app_country] => US [patent_app_date] => 2024-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5876 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18756142 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/756142
SEMICONDUCTOR DEVICE AND OPERATING METHOD THEREOF Jun 26, 2024 Pending
Array ( [id] => 19515401 [patent_doc_number] => 20240347087 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-17 [patent_title] => SEMICONDUCTOR MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/754823 [patent_app_country] => US [patent_app_date] => 2024-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 25822 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 262 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18754823 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/754823
SEMICONDUCTOR MEMORY DEVICE Jun 25, 2024 Pending
Array ( [id] => 19617255 [patent_doc_number] => 20240402935 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-05 [patent_title] => TEMPERATURE-BASED MEMORY MANAGEMENT [patent_app_type] => utility [patent_app_number] => 18/732845 [patent_app_country] => US [patent_app_date] => 2024-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 22725 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18732845 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/732845
TEMPERATURE-BASED MEMORY MANAGEMENT Jun 3, 2024 Pending
Array ( [id] => 20124262 [patent_doc_number] => 20250239293 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-24 [patent_title] => MEMORY AND OPERATION METHOD THEREOF, AND MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 18/667872 [patent_app_country] => US [patent_app_date] => 2024-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11521 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18667872 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/667872
MEMORY AND OPERATION METHOD THEREOF, AND MEMORY SYSTEM May 16, 2024 Pending
Array ( [id] => 19435771 [patent_doc_number] => 20240304269 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-12 [patent_title] => SEMICONDUCTOR DEVICE WITH SELECTIVE COMMAND DELAY AND ASSOCIATED METHODS AND SYSTEMS [patent_app_type] => utility [patent_app_number] => 18/667099 [patent_app_country] => US [patent_app_date] => 2024-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11492 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18667099 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/667099
SEMICONDUCTOR DEVICE WITH SELECTIVE COMMAND DELAY AND ASSOCIATED METHODS AND SYSTEMS May 16, 2024 Pending
Array ( [id] => 19435752 [patent_doc_number] => 20240304250 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-12 [patent_title] => ONE-LADDER READ OF MEMORY CELLS COARSELY PROGRAMMED VIA INTERLEAVED TWO-PASS DATA PROGRAMMING TECHNIQUES [patent_app_type] => utility [patent_app_number] => 18/668021 [patent_app_country] => US [patent_app_date] => 2024-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17537 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18668021 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/668021
ONE-LADDER READ OF MEMORY CELLS COARSELY PROGRAMMED VIA INTERLEAVED TWO-PASS DATA PROGRAMMING TECHNIQUES May 16, 2024 Pending
Array ( [id] => 20019286 [patent_doc_number] => 20250157508 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-15 [patent_title] => MEMORY DEVICE AND COMPUTATION METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/641578 [patent_app_country] => US [patent_app_date] => 2024-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18641578 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/641578
MEMORY DEVICE AND COMPUTATION METHOD THEREOF Apr 21, 2024 Pending
Array ( [id] => 19972219 [patent_doc_number] => 12340837 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-06-24 [patent_title] => Recognition system and SRAM cell thereof [patent_app_type] => utility [patent_app_number] => 18/629735 [patent_app_country] => US [patent_app_date] => 2024-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 16 [patent_no_of_words] => 0 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 212 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18629735 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/629735
Recognition system and SRAM cell thereof Apr 7, 2024 Issued
Array ( [id] => 20265703 [patent_doc_number] => 12436694 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-10-07 [patent_title] => Configurable memory die capacitance [patent_app_type] => utility [patent_app_number] => 18/604203 [patent_app_country] => US [patent_app_date] => 2024-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 13398 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18604203 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/604203
Configurable memory die capacitance Mar 12, 2024 Issued
Array ( [id] => 20181034 [patent_doc_number] => 20250264992 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-08-21 [patent_title] => SENSING WITHIN AN EMBEDDED DYNAMIC RANDOM ACCESS MEMORIES (DRAMS) HAVING REFERENCE CELLS [patent_app_type] => utility [patent_app_number] => 18/444816 [patent_app_country] => US [patent_app_date] => 2024-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2469 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18444816 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/444816
SENSING WITHIN AN EMBEDDED DYNAMIC RANDOM ACCESS MEMORIES (DRAMS) HAVING REFERENCE CELLS Feb 18, 2024 Pending
Array ( [id] => 19391278 [patent_doc_number] => 20240281148 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-22 [patent_title] => DYNAMIC ERASE VOLTAGE STEP [patent_app_type] => utility [patent_app_number] => 18/443584 [patent_app_country] => US [patent_app_date] => 2024-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6818 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18443584 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/443584
DYNAMIC ERASE VOLTAGE STEP Feb 15, 2024 Pending
Array ( [id] => 19687747 [patent_doc_number] => 20250006292 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-02 [patent_title] => STABLE STATE ERROR-HANDLING BIN SELECTION IN MEMORY DEVICES [patent_app_type] => utility [patent_app_number] => 18/440619 [patent_app_country] => US [patent_app_date] => 2024-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11531 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18440619 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/440619
STABLE STATE ERROR-HANDLING BIN SELECTION IN MEMORY DEVICES Feb 12, 2024 Pending
Array ( [id] => 19986735 [patent_doc_number] => 20250124957 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-04-17 [patent_title] => MEMORY DEVICE INCLUDING PIPE LATCH [patent_app_type] => utility [patent_app_number] => 18/436021 [patent_app_country] => US [patent_app_date] => 2024-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1137 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18436021 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/436021
MEMORY DEVICE INCLUDING PIPE LATCH Feb 7, 2024 Pending
Array ( [id] => 20153143 [patent_doc_number] => 20250252981 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-08-07 [patent_title] => THREE-DIMENSIONAL MEMORY DEVICE, COMPUTING CIRCUIT AND COMPUTING METHOD [patent_app_type] => utility [patent_app_number] => 18/435006 [patent_app_country] => US [patent_app_date] => 2024-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1073 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18435006 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/435006
THREE-DIMENSIONAL MEMORY DEVICE, COMPUTING CIRCUIT AND COMPUTING METHOD Feb 6, 2024 Pending
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