
Roger J. Schoeppel
Examiner (ID: 2442)
| Most Active Art Unit | 3506 |
| Art Unit(s) | 3506, 3672, 3625, 3642 |
| Total Applications | 1656 |
| Issued Applications | 1479 |
| Pending Applications | 107 |
| Abandoned Applications | 70 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 4191170
[patent_doc_number] => 06093973
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-07-25
[patent_title] => 'Hard mask for metal patterning'
[patent_app_type] => 1
[patent_app_number] => 9/163601
[patent_app_country] => US
[patent_app_date] => 1998-09-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 4
[patent_no_of_words] => 3252
[patent_no_of_claims] => 7
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[patent_words_short_claim] => 52
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/093/06093973.pdf
[firstpage_image] =>[orig_patent_app_number] => 163601
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/163601 | Hard mask for metal patterning | Sep 29, 1998 | Issued |
Array
(
[id] => 4089625
[patent_doc_number] => 06163060
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-12-19
[patent_title] => 'Semiconductor device with a composite gate dielectric layer and gate barrier layer and method of making same'
[patent_app_type] => 1
[patent_app_number] => 9/163673
[patent_app_country] => US
[patent_app_date] => 1998-09-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 3
[patent_no_of_words] => 3086
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[patent_words_short_claim] => 121
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[patent_no_of_assignments] => 0
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[firstpage_image] =>[orig_patent_app_number] => 163673
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/163673 | Semiconductor device with a composite gate dielectric layer and gate barrier layer and method of making same | Sep 29, 1998 | Issued |
Array
(
[id] => 4091027
[patent_doc_number] => 06025646
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-02-15
[patent_title] => 'Vertical MOSFET having penetrating wiring layers'
[patent_app_type] => 1
[patent_app_number] => 9/159582
[patent_app_country] => US
[patent_app_date] => 1998-09-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 6
[patent_no_of_words] => 5258
[patent_no_of_claims] => 15
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[pdf_file] => patents/06/025/06025646.pdf
[firstpage_image] =>[orig_patent_app_number] => 159582
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/159582 | Vertical MOSFET having penetrating wiring layers | Sep 23, 1998 | Issued |
Array
(
[id] => 4145186
[patent_doc_number] => 06060747
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-05-09
[patent_title] => 'Semiconductor device'
[patent_app_type] => 1
[patent_app_number] => 9/159122
[patent_app_country] => US
[patent_app_date] => 1998-09-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 7
[patent_no_of_words] => 4783
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 329
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[pdf_file] => patents/06/060/06060747.pdf
[firstpage_image] =>[orig_patent_app_number] => 159122
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/159122 | Semiconductor device | Sep 22, 1998 | Issued |
Array
(
[id] => 4056028
[patent_doc_number] => 05969390
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-10-19
[patent_title] => 'Layout solution for electromagnetic interference reduction'
[patent_app_type] => 1
[patent_app_number] => 9/158713
[patent_app_country] => US
[patent_app_date] => 1998-09-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
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[patent_no_of_words] => 1656
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[pdf_file] => patents/05/969/05969390.pdf
[firstpage_image] =>[orig_patent_app_number] => 158713
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/158713 | Layout solution for electromagnetic interference reduction | Sep 21, 1998 | Issued |
Array
(
[id] => 4108361
[patent_doc_number] => 06100566
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-08-08
[patent_title] => 'Multi-layer semiconductor device and method for fabricating the same'
[patent_app_type] => 1
[patent_app_number] => 9/157581
[patent_app_country] => US
[patent_app_date] => 1998-09-21
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[pdf_file] => patents/06/100/06100566.pdf
[firstpage_image] =>[orig_patent_app_number] => 157581
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/157581 | Multi-layer semiconductor device and method for fabricating the same | Sep 20, 1998 | Issued |
Array
(
[id] => 4137914
[patent_doc_number] => 06147408
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-11-14
[patent_title] => 'Method of forming embedded copper interconnections and embedded copper interconnection structure'
[patent_app_type] => 1
[patent_app_number] => 9/156903
[patent_app_country] => US
[patent_app_date] => 1998-09-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
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[patent_no_of_words] => 1771
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[pdf_file] => patents/06/147/06147408.pdf
[firstpage_image] =>[orig_patent_app_number] => 156903
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/156903 | Method of forming embedded copper interconnections and embedded copper interconnection structure | Sep 17, 1998 | Issued |
Array
(
[id] => 3953091
[patent_doc_number] => 05998848
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-12-07
[patent_title] => 'Depleted poly-silicon edged MOSFET structure and method'
[patent_app_type] => 1
[patent_app_number] => 9/157003
[patent_app_country] => US
[patent_app_date] => 1998-09-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
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[patent_no_of_words] => 4783
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/998/05998848.pdf
[firstpage_image] =>[orig_patent_app_number] => 157003
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/157003 | Depleted poly-silicon edged MOSFET structure and method | Sep 17, 1998 | Issued |
Array
(
[id] => 1603220
[patent_doc_number] => 06433400
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-08-13
[patent_title] => 'Semiconductor fabrication employing barrier atoms incorporated at the edges of a trench isolation structure'
[patent_app_type] => B1
[patent_app_number] => 09/153753
[patent_app_country] => US
[patent_app_date] => 1998-09-15
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/06/433/06433400.pdf
[firstpage_image] =>[orig_patent_app_number] => 09153753
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/153753 | Semiconductor fabrication employing barrier atoms incorporated at the edges of a trench isolation structure | Sep 14, 1998 | Issued |
Array
(
[id] => 4139969
[patent_doc_number] => 06121675
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-09-19
[patent_title] => 'Semiconductor optical sensing device package'
[patent_app_type] => 1
[patent_app_number] => 9/153741
[patent_app_country] => US
[patent_app_date] => 1998-09-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
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[pdf_file] => patents/06/121/06121675.pdf
[firstpage_image] =>[orig_patent_app_number] => 153741
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/153741 | Semiconductor optical sensing device package | Sep 14, 1998 | Issued |
Array
(
[id] => 3953035
[patent_doc_number] => 05998844
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-12-07
[patent_title] => 'Semiconductor constructions comprising electrically conductive plugs having monocrystalline and polycrystalline silicon'
[patent_app_type] => 1
[patent_app_number] => 9/153088
[patent_app_country] => US
[patent_app_date] => 1998-09-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
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[pdf_file] => patents/05/998/05998844.pdf
[firstpage_image] =>[orig_patent_app_number] => 153088
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/153088 | Semiconductor constructions comprising electrically conductive plugs having monocrystalline and polycrystalline silicon | Sep 13, 1998 | Issued |
Array
(
[id] => 4136844
[patent_doc_number] => 06034392
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-03-07
[patent_title] => 'Semiconductor device having capacitor'
[patent_app_type] => 1
[patent_app_number] => 9/151601
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[pdf_file] => patents/06/034/06034392.pdf
[firstpage_image] =>[orig_patent_app_number] => 151601
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/151601 | Semiconductor device having capacitor | Sep 10, 1998 | Issued |
Array
(
[id] => 3999117
[patent_doc_number] => 05920101
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-07-06
[patent_title] => 'Structure for making sub-lithographic images by the intersection of two spacers'
[patent_app_type] => 1
[patent_app_number] => 9/144806
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[patent_app_date] => 1998-09-01
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[firstpage_image] =>[orig_patent_app_number] => 144806
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/144806 | Structure for making sub-lithographic images by the intersection of two spacers | Aug 31, 1998 | Issued |
Array
(
[id] => 4264564
[patent_doc_number] => 06204521
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[patent_issue_date] => 2001-03-20
[patent_title] => 'Thin film transistors'
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[pdf_file] => patents/06/204/06204521.pdf
[firstpage_image] =>[orig_patent_app_number] => 143038
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/143038 | Thin film transistors | Aug 27, 1998 | Issued |
Array
(
[id] => 3939079
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[patent_issue_date] => 1999-08-17
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[firstpage_image] =>[orig_patent_app_number] => 143251
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/143251 | Semiconductor device and its manufacturing method | Aug 27, 1998 | Issued |
Array
(
[id] => 4145339
[patent_doc_number] => 06060757
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-05-09
[patent_title] => 'High frequency RF diode with low parasitic capacitance'
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[pdf_file] => patents/06/060/06060757.pdf
[firstpage_image] =>[orig_patent_app_number] => 140962
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/140962 | High frequency RF diode with low parasitic capacitance | Aug 26, 1998 | Issued |
Array
(
[id] => 4089727
[patent_doc_number] => 06163066
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-12-19
[patent_title] => 'Porous silicon dioxide insulator'
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[pdf_file] => patents/06/163/06163066.pdf
[firstpage_image] =>[orig_patent_app_number] => 139151
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/139151 | Porous silicon dioxide insulator | Aug 23, 1998 | Issued |
Array
(
[id] => 4038698
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[firstpage_image] =>[orig_patent_app_number] => 136612
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/136612 | Charge effect transistor and a method for manufacturing the same | Aug 19, 1998 | Issued |
Array
(
[id] => 4243793
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[patent_issue_date] => 2000-06-27
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[firstpage_image] =>[orig_patent_app_number] => 134291
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/134291 | Reduced size field effect transistor | Aug 12, 1998 | Issued |
Array
(
[id] => 4120058
[patent_doc_number] => 06046490
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[patent_title] => 'Semiconductor device having a capacitor dielectric element and wiring layers'
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[pdf_file] => patents/06/046/06046490.pdf
[firstpage_image] =>[orig_patent_app_number] => 132023
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/132023 | Semiconductor device having a capacitor dielectric element and wiring layers | Aug 9, 1998 | Issued |