
Ron Everett Pompey
Examiner (ID: 7458)
| Most Active Art Unit | 2812 |
| Art Unit(s) | 2812 |
| Total Applications | 697 |
| Issued Applications | 525 |
| Pending Applications | 9 |
| Abandoned Applications | 165 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 4597010
[patent_doc_number] => 07982227
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-07-19
[patent_title] => 'Light emitting diode package'
[patent_app_type] => utility
[patent_app_number] => 11/592192
[patent_app_country] => US
[patent_app_date] => 2006-11-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 6
[patent_no_of_words] => 2955
[patent_no_of_claims] => 9
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[patent_words_short_claim] => 253
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/982/07982227.pdf
[firstpage_image] =>[orig_patent_app_number] => 11592192
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/592192 | Light emitting diode package | Nov 2, 2006 | Issued |
Array
(
[id] => 281751
[patent_doc_number] => 07553751
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-06-30
[patent_title] => 'Method of forming solder bump with reduced surface defects'
[patent_app_type] => utility
[patent_app_number] => 11/529377
[patent_app_country] => US
[patent_app_date] => 2006-09-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
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[patent_no_of_words] => 4731
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/553/07553751.pdf
[firstpage_image] =>[orig_patent_app_number] => 11529377
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/529377 | Method of forming solder bump with reduced surface defects | Sep 28, 2006 | Issued |
Array
(
[id] => 5242425
[patent_doc_number] => 20070020920
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-01-25
[patent_title] => 'Method for fabricating low leakage interconnect layers in integrated circuits'
[patent_app_type] => utility
[patent_app_number] => 11/525428
[patent_app_country] => US
[patent_app_date] => 2006-09-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 15
[patent_no_of_words] => 7966
[patent_no_of_claims] => 28
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0020/20070020920.pdf
[firstpage_image] =>[orig_patent_app_number] => 11525428
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/525428 | Method for fabricating low leakage interconnect layers in integrated circuits | Sep 21, 2006 | Abandoned |
Array
(
[id] => 5242281
[patent_doc_number] => 20070020776
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-01-25
[patent_title] => 'Method and apparatus for wall film monitoring'
[patent_app_type] => utility
[patent_app_number] => 11/517389
[patent_app_country] => US
[patent_app_date] => 2006-09-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 4818
[patent_no_of_claims] => 3
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[pdf_file] => publications/A1/0020/20070020776.pdf
[firstpage_image] =>[orig_patent_app_number] => 11517389
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/517389 | Method and apparatus for wall film monitoring | Sep 7, 2006 | Issued |
Array
(
[id] => 5098668
[patent_doc_number] => 20070181928
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-08-09
[patent_title] => 'Capacitor and manufacturing method thereof'
[patent_app_type] => utility
[patent_app_number] => 11/508141
[patent_app_country] => US
[patent_app_date] => 2006-08-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
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[patent_no_of_words] => 5029
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[pdf_file] => publications/A1/0181/20070181928.pdf
[firstpage_image] =>[orig_patent_app_number] => 11508141
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/508141 | Capacitor and manufacturing method thereof | Aug 22, 2006 | Issued |
Array
(
[id] => 4999905
[patent_doc_number] => 20070042539
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-02-22
[patent_title] => 'Method of manufacturing a non-volatile memory device'
[patent_app_type] => utility
[patent_app_number] => 11/504422
[patent_app_country] => US
[patent_app_date] => 2006-08-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
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[patent_no_of_words] => 7612
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[pdf_file] => publications/A1/0042/20070042539.pdf
[firstpage_image] =>[orig_patent_app_number] => 11504422
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/504422 | Method of manufacturing a non-volatile memory device | Aug 14, 2006 | Abandoned |
Array
(
[id] => 4574888
[patent_doc_number] => 07859042
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-12-28
[patent_title] => 'Nonvolatile memory devices'
[patent_app_type] => utility
[patent_app_number] => 11/499268
[patent_app_country] => US
[patent_app_date] => 2006-08-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 19
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/859/07859042.pdf
[firstpage_image] =>[orig_patent_app_number] => 11499268
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/499268 | Nonvolatile memory devices | Aug 3, 2006 | Issued |
Array
(
[id] => 5242375
[patent_doc_number] => 20070020870
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-01-25
[patent_title] => 'Semiconductor capacitor structure and method to form same'
[patent_app_type] => utility
[patent_app_number] => 11/495655
[patent_app_country] => US
[patent_app_date] => 2006-07-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
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[patent_no_of_words] => 1534
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[pdf_file] => publications/A1/0020/20070020870.pdf
[firstpage_image] =>[orig_patent_app_number] => 11495655
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/495655 | Semiconductor capacitor structure and method to form same | Jul 27, 2006 | Issued |
Array
(
[id] => 291780
[patent_doc_number] => 07544069
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-06-09
[patent_title] => 'Method for fabricating thin film pattern and method for fabricating flat panel display device using the same'
[patent_app_type] => utility
[patent_app_number] => 11/494632
[patent_app_country] => US
[patent_app_date] => 2006-07-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 21
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[patent_no_of_words] => 5198
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/544/07544069.pdf
[firstpage_image] =>[orig_patent_app_number] => 11494632
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/494632 | Method for fabricating thin film pattern and method for fabricating flat panel display device using the same | Jul 27, 2006 | Issued |
Array
(
[id] => 4657666
[patent_doc_number] => 20080026527
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-01-31
[patent_title] => 'AN APPARATUS AND ASSOCIATED METHOD FOR MAKING A FLOATING GATE MEMORY DEVICE WITH INCREASED GATE COUPLING RATIO'
[patent_app_type] => utility
[patent_app_number] => 11/460216
[patent_app_country] => US
[patent_app_date] => 2006-07-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 2960
[patent_no_of_claims] => 39
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0026/20080026527.pdf
[firstpage_image] =>[orig_patent_app_number] => 11460216
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/460216 | Apparatus and associated method for making a floating gate memory device with buried diffusion dielectric structures and increased gate coupling ratio | Jul 25, 2006 | Issued |
Array
(
[id] => 5625441
[patent_doc_number] => 20060263946
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-11-23
[patent_title] => 'Recessed gate dielectric antifuse'
[patent_app_type] => utility
[patent_app_number] => 11/492620
[patent_app_country] => US
[patent_app_date] => 2006-07-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
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[patent_no_of_words] => 4273
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[pdf_file] => publications/A1/0263/20060263946.pdf
[firstpage_image] =>[orig_patent_app_number] => 11492620
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/492620 | Recessed gate dielectric antifuse | Jul 24, 2006 | Issued |
Array
(
[id] => 5733000
[patent_doc_number] => 20060258117
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-11-16
[patent_title] => 'Dry etching method, fabrication method for semiconductor device, and dry etching apparatus'
[patent_app_type] => utility
[patent_app_number] => 11/487968
[patent_app_country] => US
[patent_app_date] => 2006-07-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
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[pdf_file] => publications/A1/0258/20060258117.pdf
[firstpage_image] =>[orig_patent_app_number] => 11487968
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/487968 | Dry etching method, fabrication method for semiconductor device, and dry etching apparatus | Jul 17, 2006 | Issued |
Array
(
[id] => 5661615
[patent_doc_number] => 20060252211
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[patent_kind] => A1
[patent_issue_date] => 2006-11-09
[patent_title] => 'ATOMIC LAYER DEPOSITED NANOLAMINATES OF HfO2/ZrO2 FILMS AS GATE DIELECTRICS'
[patent_app_type] => utility
[patent_app_number] => 11/457978
[patent_app_country] => US
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[patent_effective_date] => 0000-00-00
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[pdf_file] => publications/A1/0252/20060252211.pdf
[firstpage_image] =>[orig_patent_app_number] => 11457978
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/457978 | ATOMIC LAYER DEPOSITED NANOLAMINATES OF HfO2/ZrO2 FILMS AS GATE DIELECTRICS | Jul 16, 2006 | Abandoned |
Array
(
[id] => 5834910
[patent_doc_number] => 20060246741
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[patent_kind] => A1
[patent_issue_date] => 2006-11-02
[patent_title] => 'ATOMIC LAYER DEPOSITED NANOLAMINATES OF HfO2/ZrO2 FILMS AS GATE DIELECTRICS'
[patent_app_type] => utility
[patent_app_number] => 11/457987
[patent_app_country] => US
[patent_app_date] => 2006-07-17
[patent_effective_date] => 0000-00-00
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/457987 | ATOMIC LAYER DEPOSITED NANOLAMINATES OF HfO2/ZrO2 FILMS AS GATE DIELECTRICS | Jul 16, 2006 | Abandoned |
Array
(
[id] => 4803122
[patent_doc_number] => 20080014710
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-01-17
[patent_title] => 'Isolation regions'
[patent_app_type] => utility
[patent_app_number] => 11/486691
[patent_app_country] => US
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[firstpage_image] =>[orig_patent_app_number] => 11486691
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/486691 | Isolation regions | Jul 13, 2006 | Issued |
Array
(
[id] => 151282
[patent_doc_number] => 07682874
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-03-23
[patent_title] => 'Chip scale package (CSP) assembly apparatus and method'
[patent_app_type] => utility
[patent_app_number] => 11/483861
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[patent_app_date] => 2006-07-10
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/483861 | Chip scale package (CSP) assembly apparatus and method | Jul 9, 2006 | Issued |
Array
(
[id] => 4803121
[patent_doc_number] => 20080014709
[patent_country] => US
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[patent_issue_date] => 2008-01-17
[patent_title] => 'Method and apparatus for electroprocessing a substrate with edge profile control'
[patent_app_type] => utility
[patent_app_number] => 11/483843
[patent_app_country] => US
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/483843 | Method and apparatus for electroprocessing a substrate with edge profile control | Jul 6, 2006 | Issued |
Array
(
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/480841 | Package module having a stacking platform | Jul 5, 2006 | Abandoned |
Array
(
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[patent_title] => 'Submount of semiconductor laser diode, method of manufacturing the same, and semiconductor laser diode assembly using the submount'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/477911 | Submount of semiconductor laser diode, method of manufacturing the same, and semiconductor laser diode assembly using the submount | Jun 29, 2006 | Abandoned |
Array
(
[id] => 7590955
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[patent_title] => 'Inlet for an electronic tag'
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[patent_app_number] => 11/453898
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[firstpage_image] =>[orig_patent_app_number] => 11453898
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/453898 | Inlet for an electronic tag | Jun 15, 2006 | Issued |