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Ron Everett Pompey

Examiner (ID: 18586)

Most Active Art Unit
2812
Art Unit(s)
2812
Total Applications
697
Issued Applications
525
Pending Applications
9
Abandoned Applications
165

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 8403180 [patent_doc_number] => 20120235237 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-09-20 [patent_title] => 'METHODS FOR FORMING BARRIER REGIONS WITHIN REGIONS OF INSULATING MATERIAL RESULTING IN OUTGASSING PATHS FROM THE INSULATING MATERIAL AND RELATED DEVICES' [patent_app_type] => utility [patent_app_number] => 13/488109 [patent_app_country] => US [patent_app_date] => 2012-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5730 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13488109 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/488109
Methods for forming barrier regions within regions of insulating material resulting in outgassing paths from the insulating material and related devices Jun 3, 2012 Issued
Array ( [id] => 8390418 [patent_doc_number] => 20120228260 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-09-13 [patent_title] => 'PROCESS FOR ETCHING TRENCHES IN AN INTEGRATED OPTICAL DEVICE' [patent_app_type] => utility [patent_app_number] => 13/481680 [patent_app_country] => US [patent_app_date] => 2012-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3028 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13481680 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/481680
Process for etching trenches in an integrated optical device May 24, 2012 Issued
Array ( [id] => 10838523 [patent_doc_number] => 08866202 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-10-21 [patent_title] => 'Device with gaps for capacitance reduction' [patent_app_type] => utility [patent_app_number] => 13/457147 [patent_app_country] => US [patent_app_date] => 2012-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 21 [patent_no_of_words] => 4576 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13457147 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/457147
Device with gaps for capacitance reduction Apr 25, 2012 Issued
Array ( [id] => 8592393 [patent_doc_number] => 08350269 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-01-08 [patent_title] => 'Semiconductor-on-insulator (SOI) structure and method of forming the SOI structure using a bulk semiconductor starting wafer' [patent_app_type] => utility [patent_app_number] => 13/455174 [patent_app_country] => US [patent_app_date] => 2012-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 15 [patent_no_of_words] => 7501 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13455174 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/455174
Semiconductor-on-insulator (SOI) structure and method of forming the SOI structure using a bulk semiconductor starting wafer Apr 24, 2012 Issued
Array ( [id] => 8345774 [patent_doc_number] => 20120206668 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-08-16 [patent_title] => 'THIN-FILM TRANSISTOR DEVICE MANUFACTURING METHOD, THIN-FILM TRANSISTOR, AND DISPLAY DEVICE' [patent_app_type] => utility [patent_app_number] => 13/455375 [patent_app_country] => US [patent_app_date] => 2012-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 27 [patent_no_of_words] => 21147 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13455375 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/455375
Thin-film transistor device manufacturing method, thin-film transistor, and display device Apr 24, 2012 Issued
Array ( [id] => 8920840 [patent_doc_number] => 08486772 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-07-16 [patent_title] => 'Method of manufacturing SOI substrate' [patent_app_type] => utility [patent_app_number] => 13/454114 [patent_app_country] => US [patent_app_date] => 2012-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 26 [patent_no_of_words] => 9555 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13454114 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/454114
Method of manufacturing SOI substrate Apr 23, 2012 Issued
Array ( [id] => 8333108 [patent_doc_number] => 20120199815 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-08-09 [patent_title] => 'SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 13/453125 [patent_app_country] => US [patent_app_date] => 2012-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 9522 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13453125 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/453125
Semiconductor device and method of manufacturing the same Apr 22, 2012 Issued
Array ( [id] => 9496421 [patent_doc_number] => 08735233 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-05-27 [patent_title] => 'Manufacturing method for thin film semiconductor device, manufacturing method for thin film semiconductor array substrate, method of forming crystalline silicon thin film, and apparatus for forming crystalline silicon thin film' [patent_app_type] => utility [patent_app_number] => 13/451078 [patent_app_country] => US [patent_app_date] => 2012-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 16 [patent_no_of_words] => 13648 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 246 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13451078 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/451078
Manufacturing method for thin film semiconductor device, manufacturing method for thin film semiconductor array substrate, method of forming crystalline silicon thin film, and apparatus for forming crystalline silicon thin film Apr 18, 2012 Issued
Array ( [id] => 8323981 [patent_doc_number] => 20120196392 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-08-02 [patent_title] => 'PIXEL DESIGNS OF IMPROVING THE APERTURE RATIO IN AN LCD' [patent_app_type] => utility [patent_app_number] => 13/443672 [patent_app_country] => US [patent_app_date] => 2012-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4281 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13443672 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/443672
Pixel designs of improving the aperture ratio in an LCD Apr 9, 2012 Issued
Array ( [id] => 8788829 [patent_doc_number] => 20130105797 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-05-02 [patent_title] => 'THIN-FILM SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 13/440320 [patent_app_country] => US [patent_app_date] => 2012-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 16771 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13440320 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/440320
Thin-film semiconductor device and method of manufacturing the same Apr 4, 2012 Issued
Array ( [id] => 8301540 [patent_doc_number] => 20120184104 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-07-19 [patent_title] => 'METHOD FOR FABRICATING FINE PATTERN IN SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 13/427485 [patent_app_country] => US [patent_app_date] => 2012-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2463 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13427485 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/427485
METHOD FOR FABRICATING FINE PATTERN IN SEMICONDUCTOR DEVICE Mar 21, 2012 Abandoned
Array ( [id] => 8708093 [patent_doc_number] => 20130065382 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-03-14 [patent_title] => 'METHOD OF MANUFACTURING SILICON CARBIDE SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 13/407249 [patent_app_country] => US [patent_app_date] => 2012-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4951 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13407249 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/407249
Method of manufacturing silicon carbide semiconductor device Feb 27, 2012 Issued
Array ( [id] => 8379778 [patent_doc_number] => 20120223407 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-09-06 [patent_title] => 'Superior Integrity of High-K Metal Gate Stacks by Capping STI Regions' [patent_app_type] => utility [patent_app_number] => 13/406869 [patent_app_country] => US [patent_app_date] => 2012-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7961 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13406869 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/406869
Superior integrity of high-k metal gate stacks by capping STI regions Feb 27, 2012 Issued
Array ( [id] => 9762151 [patent_doc_number] => 08846472 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-09-30 [patent_title] => 'Method for fabricating semiconductor device' [patent_app_type] => utility [patent_app_number] => 13/406739 [patent_app_country] => US [patent_app_date] => 2012-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 19 [patent_no_of_words] => 3913 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13406739 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/406739
Method for fabricating semiconductor device Feb 27, 2012 Issued
Array ( [id] => 8335652 [patent_doc_number] => 20120202358 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-08-09 [patent_title] => 'GRADED DIELECTRIC STRUCTURES' [patent_app_type] => utility [patent_app_number] => 13/366025 [patent_app_country] => US [patent_app_date] => 2012-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 8223 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13366025 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/366025
Graded dielectric structures Feb 2, 2012 Issued
Array ( [id] => 8159458 [patent_doc_number] => 20120100714 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-04-26 [patent_title] => 'Method of Fabricating a Landing Plug in a Semiconductor Device' [patent_app_type] => utility [patent_app_number] => 13/342815 [patent_app_country] => US [patent_app_date] => 2012-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3449 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0100/20120100714.pdf [firstpage_image] =>[orig_patent_app_number] => 13342815 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/342815
Method of fabricating a landing plug in a semiconductor device Jan 2, 2012 Issued
Array ( [id] => 8652964 [patent_doc_number] => 08372710 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-02-12 [patent_title] => 'Vertical transistors' [patent_app_type] => utility [patent_app_number] => 13/329977 [patent_app_country] => US [patent_app_date] => 2011-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 35 [patent_no_of_words] => 11422 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13329977 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/329977
Vertical transistors Dec 18, 2011 Issued
Array ( [id] => 8405988 [patent_doc_number] => 20120238045 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-09-20 [patent_title] => 'THREE DIMENSIONAL LIGHT EMITTING DIODE SYSTEMS, AND COMPOSITIONS AND METHODS RELATING THERETO' [patent_app_type] => utility [patent_app_number] => 13/326619 [patent_app_country] => US [patent_app_date] => 2011-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 11381 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13326619 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/326619
THREE DIMENSIONAL LIGHT EMITTING DIODE SYSTEMS, AND COMPOSITIONS AND METHODS RELATING THERETO Dec 14, 2011 Abandoned
Array ( [id] => 8489610 [patent_doc_number] => 20120289017 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-11-15 [patent_title] => 'METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 13/326275 [patent_app_country] => US [patent_app_date] => 2011-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3802 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13326275 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/326275
Method of manufacturing semiconductor device including ashing of photoresist with deuterium or tritium gas Dec 13, 2011 Issued
Array ( [id] => 8733232 [patent_doc_number] => 20130078801 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-03-28 [patent_title] => 'MANUFACTURE METHODS OF DOUBLE LAYER GATE ELECTRODE AND RELEVANT THIN FILM TRANSISTOR' [patent_app_type] => utility [patent_app_number] => 13/378046 [patent_app_country] => US [patent_app_date] => 2011-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3479 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13378046 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/378046
MANUFACTURE METHODS OF DOUBLE LAYER GATE ELECTRODE AND RELEVANT THIN FILM TRANSISTOR Oct 6, 2011 Abandoned
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