Search

Ron Everett Pompey

Examiner (ID: 7458)

Most Active Art Unit
2812
Art Unit(s)
2812
Total Applications
697
Issued Applications
525
Pending Applications
9
Abandoned Applications
165

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 8955841 [patent_doc_number] => 08501613 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-08-06 [patent_title] => 'UBM etching methods for eliminating undercut' [patent_app_type] => utility [patent_app_number] => 13/178276 [patent_app_country] => US [patent_app_date] => 2011-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 2464 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13178276 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/178276
UBM etching methods for eliminating undercut Jul 6, 2011 Issued
Array ( [id] => 8265399 [patent_doc_number] => 20120164824 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-06-28 [patent_title] => 'METHOD FOR FABRICATING A HIGH-K METAL GATE MOS' [patent_app_type] => utility [patent_app_number] => 13/178455 [patent_app_country] => US [patent_app_date] => 2011-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3717 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13178455 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/178455
Method for fabricating a high-K metal gate MOS Jul 6, 2011 Issued
Array ( [id] => 9875133 [patent_doc_number] => 08962400 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-02-24 [patent_title] => 'In-situ doping of arsenic for source and drain epitaxy' [patent_app_type] => utility [patent_app_number] => 13/178294 [patent_app_country] => US [patent_app_date] => 2011-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 13 [patent_no_of_words] => 2431 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13178294 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/178294
In-situ doping of arsenic for source and drain epitaxy Jul 6, 2011 Issued
Array ( [id] => 9590055 [patent_doc_number] => 08779598 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-07-15 [patent_title] => 'Method and apparatuses for integrated circuit substrate manufacture' [patent_app_type] => utility [patent_app_number] => 13/170820 [patent_app_country] => US [patent_app_date] => 2011-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3192 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13170820 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/170820
Method and apparatuses for integrated circuit substrate manufacture Jun 27, 2011 Issued
Array ( [id] => 8563591 [patent_doc_number] => 20120326162 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-12-27 [patent_title] => 'PROCESS FOR FORMING REPAIR LAYER AND MOS TRANSISTOR HAVING REPAIR LAYER' [patent_app_type] => utility [patent_app_number] => 13/169129 [patent_app_country] => US [patent_app_date] => 2011-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2276 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13169129 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/169129
Process for forming repair layer and MOS transistor having repair layer Jun 26, 2011 Issued
Array ( [id] => 9869735 [patent_doc_number] => 08957509 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-02-17 [patent_title] => 'Integrated circuit packaging system with thermal emission and method of manufacture thereof' [patent_app_type] => utility [patent_app_number] => 13/166809 [patent_app_country] => US [patent_app_date] => 2011-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 58 [patent_no_of_words] => 17951 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13166809 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/166809
Integrated circuit packaging system with thermal emission and method of manufacture thereof Jun 22, 2011 Issued
Array ( [id] => 8071853 [patent_doc_number] => 20110241096 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-10-06 [patent_title] => 'ISOLATION REGIONS' [patent_app_type] => utility [patent_app_number] => 13/164085 [patent_app_country] => US [patent_app_date] => 2011-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4433 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0241/20110241096.pdf [firstpage_image] =>[orig_patent_app_number] => 13164085 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/164085
Isolation regions Jun 19, 2011 Issued
Array ( [id] => 8340640 [patent_doc_number] => 08242567 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-08-14 [patent_title] => 'Semiconductor device and manufacturing method thereof' [patent_app_type] => utility [patent_app_number] => 13/117786 [patent_app_country] => US [patent_app_date] => 2011-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 34 [patent_no_of_words] => 17552 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13117786 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/117786
Semiconductor device and manufacturing method thereof May 26, 2011 Issued
Array ( [id] => 8909338 [patent_doc_number] => 08481401 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-07-09 [patent_title] => 'Component having a through-contact' [patent_app_type] => utility [patent_app_number] => 13/134075 [patent_app_country] => US [patent_app_date] => 2011-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5343 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13134075 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/134075
Component having a through-contact May 25, 2011 Issued
Array ( [id] => 8393747 [patent_doc_number] => 20120231588 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-09-13 [patent_title] => 'MANUFACTURING METHOD OF THIN FILM TRANSISTOR' [patent_app_type] => utility [patent_app_number] => 13/117130 [patent_app_country] => US [patent_app_date] => 2011-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4305 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13117130 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/117130
MANUFACTURING METHOD OF THIN FILM TRANSISTOR May 25, 2011 Abandoned
Array ( [id] => 7662910 [patent_doc_number] => 20110312179 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-12-22 [patent_title] => 'SUBSTRATE PROCESSING METHOD AND SUBSTRATE PROCESSING APPARATUS' [patent_app_type] => utility [patent_app_number] => 13/115410 [patent_app_country] => US [patent_app_date] => 2011-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7611 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0312/20110312179.pdf [firstpage_image] =>[orig_patent_app_number] => 13115410 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/115410
SUBSTRATE PROCESSING METHOD AND SUBSTRATE PROCESSING APPARATUS May 24, 2011 Abandoned
Array ( [id] => 6014629 [patent_doc_number] => 20110223080 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-09-15 [patent_title] => 'FLUIDIC DEVICE CONTAINING 3D STRUCTURES' [patent_app_type] => utility [patent_app_number] => 13/114419 [patent_app_country] => US [patent_app_date] => 2011-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4083 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0223/20110223080.pdf [firstpage_image] =>[orig_patent_app_number] => 13114419 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/114419
FLUIDIC DEVICE CONTAINING 3D STRUCTURES May 23, 2011 Abandoned
Array ( [id] => 8465243 [patent_doc_number] => 20120270411 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-10-25 [patent_title] => 'MANUFACTURING METHOD OF GATE DIELECTRIC LAYER' [patent_app_type] => utility [patent_app_number] => 13/092994 [patent_app_country] => US [patent_app_date] => 2011-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1312 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13092994 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/092994
MANUFACTURING METHOD OF GATE DIELECTRIC LAYER Apr 24, 2011 Abandoned
Array ( [id] => 7510980 [patent_doc_number] => 20110256690 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-10-20 [patent_title] => 'INTEGRATED CIRCUIT WAFER DICING METHOD' [patent_app_type] => utility [patent_app_number] => 13/089472 [patent_app_country] => US [patent_app_date] => 2011-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 1586 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0256/20110256690.pdf [firstpage_image] =>[orig_patent_app_number] => 13089472 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/089472
INTEGRATED CIRCUIT WAFER DICING METHOD Apr 18, 2011 Abandoned
Array ( [id] => 8802264 [patent_doc_number] => 08440538 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-05-14 [patent_title] => 'Method of manufacturing airbridge' [patent_app_type] => utility [patent_app_number] => 13/089343 [patent_app_country] => US [patent_app_date] => 2011-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 15 [patent_no_of_words] => 7047 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 254 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13089343 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/089343
Method of manufacturing airbridge Apr 18, 2011 Issued
Array ( [id] => 6189066 [patent_doc_number] => 20110171785 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-07-14 [patent_title] => 'METHOD OF MAKING A SEMICONDUCTOR CHIP ASSEMBLY WITH A BUMP/BASE HEAT SPREADER AND AN INVERTED CAVITY IN THE BUMP' [patent_app_type] => utility [patent_app_number] => 13/052073 [patent_app_country] => US [patent_app_date] => 2011-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 43 [patent_figures_cnt] => 43 [patent_no_of_words] => 30823 [patent_no_of_claims] => 71 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0171/20110171785.pdf [firstpage_image] =>[orig_patent_app_number] => 13052073 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/052073
Method of making a semiconductor chip assembly with a bump/base heat spreader and an inverted cavity in the bump Mar 19, 2011 Issued
Array ( [id] => 6097171 [patent_doc_number] => 20110162633 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-07-07 [patent_title] => 'HEAT TREATMENT METHOD AND HEAT TREATMENT APPARATUS' [patent_app_type] => utility [patent_app_number] => 12/987406 [patent_app_country] => US [patent_app_date] => 2011-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 15221 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0162/20110162633.pdf [firstpage_image] =>[orig_patent_app_number] => 12987406 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/987406
Heat treatment method and heat treatment apparatus wherein the substrate holder is composed of two holder constituting bodies that move relative to each other Jan 9, 2011 Issued
Array ( [id] => 7811245 [patent_doc_number] => 08133775 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-03-13 [patent_title] => 'Semiconductor device with mushroom electrode and manufacture method thereof' [patent_app_type] => utility [patent_app_number] => 12/985742 [patent_app_country] => US [patent_app_date] => 2011-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 44 [patent_no_of_words] => 8211 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 257 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/133/08133775.pdf [firstpage_image] =>[orig_patent_app_number] => 12985742 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/985742
Semiconductor device with mushroom electrode and manufacture method thereof Jan 5, 2011 Issued
Array ( [id] => 6119762 [patent_doc_number] => 20110076851 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-03-31 [patent_title] => 'METHOD FOR FABRICATING FINE PATTERN IN SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 12/962307 [patent_app_country] => US [patent_app_date] => 2010-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2352 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0076/20110076851.pdf [firstpage_image] =>[orig_patent_app_number] => 12962307 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/962307
Method for fabricating fine pattern in semiconductor device Dec 6, 2010 Issued
Array ( [id] => 8146600 [patent_doc_number] => 08163608 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-04-24 [patent_title] => 'Methods of fabricating nonvolatile memory devices' [patent_app_type] => utility [patent_app_number] => 12/949870 [patent_app_country] => US [patent_app_date] => 2010-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 32 [patent_no_of_words] => 10670 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/163/08163608.pdf [firstpage_image] =>[orig_patent_app_number] => 12949870 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/949870
Methods of fabricating nonvolatile memory devices Nov 18, 2010 Issued
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