Ronald Lance Reidlinger

Array ( [id] => 6348476 [patent_doc_number] => 20100085799 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-04-08 [patent_title] => 'METHOD OF DRIVING MULTI-LEVEL VARIABLE RESISTIVE MEMORY DEVICE AND MULTI-LEVEL VARIABLE RESISTIVE MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 12/632018 [patent_app_country] => US [patent_app_date] => 2009-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 35 [patent_figures_cnt] => 35 [patent_no_of_words] => 13979 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0085/20100085799.pdf [firstpage_image] =>[orig_patent_app_number] => 12632018 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6368125 [patent_doc_number] => 20100080042 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-04-01 [patent_title] => 'INTEGRATING NONVOLATILE MEMORY CAPABILITY WITHIN SRAM DEVICES' [patent_app_type] => utility [patent_app_number] => 12/631900 [patent_app_country] => US [patent_app_date] => 2009-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4450 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0080/20100080042.pdf [firstpage_image] =>[orig_patent_app_number] => 12631900 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9287726 [patent_doc_number] => 08644066 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-02-04 [patent_title] => 'Multi-level non-volatile memory device, system and method with state-converted data' [patent_app_type] => utility [patent_app_number] => 12/620907 [patent_app_country] => US [patent_app_date] => 2009-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 9119 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12620907 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6310153 [patent_doc_number] => 20100110796 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-05-06 [patent_title] => 'METHOD OF PERFORMING ERASE OPERATION IN NON-VOLATILE MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 12/609127 [patent_app_country] => US [patent_app_date] => 2009-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8882 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0110/20100110796.pdf [firstpage_image] =>[orig_patent_app_number] => 12609127 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8318524 [patent_doc_number] => 08233309 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-07-31 [patent_title] => 'Non-volatile memory array architecture incorporating 1T-1R near 4F2 memory cell' [patent_app_type] => utility [patent_app_number] => 12/606111 [patent_app_country] => US [patent_app_date] => 2009-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 14 [patent_no_of_words] => 8123 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 251 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12606111 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6309961 [patent_doc_number] => 20100110751 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-05-06 [patent_title] => 'SEMICONDUCTOR STORAGE DEVICE' [patent_app_type] => utility [patent_app_number] => 12/603623 [patent_app_country] => US [patent_app_date] => 2009-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 5239 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0110/20100110751.pdf [firstpage_image] =>[orig_patent_app_number] => 12603623 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6469998 [patent_doc_number] => 20100091541 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-04-15 [patent_title] => 'Stacked memory device and method thereof' [patent_app_type] => utility [patent_app_number] => 12/588275 [patent_app_country] => US [patent_app_date] => 2009-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 5315 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0091/20100091541.pdf [firstpage_image] =>[orig_patent_app_number] => 12588275 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9377288 [patent_doc_number] => 08681558 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-03-25 [patent_title] => 'Parallel bitline nonvolatile memory employing channel-based processing technology' [patent_app_type] => utility [patent_app_number] => 12/575137 [patent_app_country] => US [patent_app_date] => 2009-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 10389 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12575137 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6117759 [patent_doc_number] => 20110075482 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-03-31 [patent_title] => 'MAINTAINING INTEGRITY OF PRELOADED CONTENT IN NON-VOLATILE MEMORY DURING SURFACE MOUNTING' [patent_app_type] => utility [patent_app_number] => 12/569869 [patent_app_country] => US [patent_app_date] => 2009-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 8613 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0075/20110075482.pdf [firstpage_image] =>[orig_patent_app_number] => 12569869 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5974518 [patent_doc_number] => 20110069560 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-03-24 [patent_title] => 'DATA CAPTURE SYSTEM AND METHOD, AND MEMORY CONTROLLERS AND DEVICES' [patent_app_type] => utility [patent_app_number] => 12/565655 [patent_app_country] => US [patent_app_date] => 2009-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3426 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0069/20110069560.pdf [firstpage_image] =>[orig_patent_app_number] => 12565655 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8654261 [patent_doc_number] => 08374017 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-02-12 [patent_title] => 'Ferroelectric memory device and method with reference potential correction capacitor(s)' [patent_app_type] => utility [patent_app_number] => 12/559447 [patent_app_country] => US [patent_app_date] => 2009-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 5742 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12559447 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5366244 [patent_doc_number] => 20090303803 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-12-10 [patent_title] => 'Independent Bi-Directional Margin Control Per Level and Independently Expandable Reference Cell Levels for Voltage Mode Sensing' [patent_app_type] => utility [patent_app_number] => 12/543424 [patent_app_country] => US [patent_app_date] => 2009-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 7492 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0303/20090303803.pdf [firstpage_image] =>[orig_patent_app_number] => 12543424 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5366257 [patent_doc_number] => 20090303816 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-12-10 [patent_title] => 'SEMICONDUCTOR MEMORY APPARATUS AND METHOD OF CONTROLLING REDUNDANCY THEREOF' [patent_app_type] => utility [patent_app_number] => 12/541683 [patent_app_country] => US [patent_app_date] => 2009-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3402 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0303/20090303816.pdf [firstpage_image] =>[orig_patent_app_number] => 12541683 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6616335 [patent_doc_number] => 20100034026 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-02-11 [patent_title] => 'ERASE METHOD AND NON-VOLATILE SEMICONDUCTOR MEMORY' [patent_app_type] => utility [patent_app_number] => 12/535903 [patent_app_country] => US [patent_app_date] => 2009-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3292 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0034/20100034026.pdf [firstpage_image] =>[orig_patent_app_number] => 12535903 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9846001 [patent_doc_number] => 08947927 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-02-03 [patent_title] => 'Gated diode memory cells' [patent_app_type] => utility [patent_app_number] => 12/512559 [patent_app_country] => US [patent_app_date] => 2009-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 54 [patent_no_of_words] => 11522 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12512559 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6616067 [patent_doc_number] => 20100034006 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-02-11 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 12/501705 [patent_app_country] => US [patent_app_date] => 2009-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 6685 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0034/20100034006.pdf [firstpage_image] =>[orig_patent_app_number] => 12501705 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6316463 [patent_doc_number] => 20100195377 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-08-05 [patent_title] => 'SEMICONDUCTOR MEMORY APPARATUS AND METHOD OF TESTING THE SAME' [patent_app_type] => utility [patent_app_number] => 12/494511 [patent_app_country] => US [patent_app_date] => 2009-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2914 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0195/20100195377.pdf [firstpage_image] =>[orig_patent_app_number] => 12494511 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6403754 [patent_doc_number] => 20100165750 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-07-01 [patent_title] => 'DATA INPUT DEVICE OF SEMICONDUCTOR MEMORY APPARTUS AND CONTROL METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 12/490859 [patent_app_country] => US [patent_app_date] => 2009-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3916 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0165/20100165750.pdf [firstpage_image] =>[orig_patent_app_number] => 12490859 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6588054 [patent_doc_number] => 20100321987 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-12-23 [patent_title] => 'MEMORY DEVICE AND METHOD FOR SENSING AND FIXING MARGIN CELLS' [patent_app_type] => utility [patent_app_number] => 12/488995 [patent_app_country] => US [patent_app_date] => 2009-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7603 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0321/20100321987.pdf [firstpage_image] =>[orig_patent_app_number] => 12488995 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6590086 [patent_doc_number] => 20100001267 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-01-07 [patent_title] => 'NRAM ARRAYS WITH NANOTUBE BLOCKS, NANOTUBE TRACES, AND NANOTUBE PLANES AND METHODS OF MAKING SAME' [patent_app_type] => utility [patent_app_number] => 12/486602 [patent_app_country] => US [patent_app_date] => 2009-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 48 [patent_figures_cnt] => 48 [patent_no_of_words] => 26243 [patent_no_of_claims] => 57 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12486602 [rel_patent_id] =>[rel_patent_doc_number] =>)