
Ronald Lance Reidlinger
Examiner (ID: 7236, Phone: (571)270-7353 , Office: P/2824 )
| Most Active Art Unit | 2824 |
| Art Unit(s) | 4134, 2824 |
| Total Applications | 515 |
| Issued Applications | 439 |
| Pending Applications | 0 |
| Abandoned Applications | 77 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
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[patent_title] => 'SYSTEMS AND METHODS FOR WIRE FEED SPEED CONTROL'
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Array
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[patent_title] => 'CES-based latching circuits'
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[patent_title] => 'SYSTEM AND METHOD FOR HANDING OFF THE CONFIGURATION OF A BUILDING DEVICE FROM A CONTRACTOR TO A CUSTOMER USING A HANG TAG OR THE LIKE'
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Array
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Array
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Array
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[patent_title] => 'Encoded Global Bitlines for Memory and Other Circuits'
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Array
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Array
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