Search

Ronald Lance Reidlinger

Examiner (ID: 7236, Phone: (571)270-7353 , Office: P/2824 )

Most Active Art Unit
2824
Art Unit(s)
4134, 2824
Total Applications
515
Issued Applications
439
Pending Applications
0
Abandoned Applications
77

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 10979030 [patent_doc_number] => 20160175973 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-06-23 [patent_title] => 'SYSTEMS AND METHODS FOR WIRE FEED SPEED CONTROL' [patent_app_type] => utility [patent_app_number] => 15/056661 [patent_app_country] => US [patent_app_date] => 2016-02-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3759 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15056661 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/056661
Systems and methods for wire feed speed control Feb 28, 2016 Issued
Array ( [id] => 11918179 [patent_doc_number] => 09786370 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-10-10 [patent_title] => 'CES-based latching circuits' [patent_app_type] => utility [patent_app_number] => 15/051359 [patent_app_country] => US [patent_app_date] => 2016-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 19430 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15051359 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/051359
CES-based latching circuits Feb 22, 2016 Issued
Array ( [id] => 11517245 [patent_doc_number] => 20170084319 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-23 [patent_title] => 'BIT LINE EQUALIZER' [patent_app_type] => utility [patent_app_number] => 15/047408 [patent_app_country] => US [patent_app_date] => 2016-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 3636 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15047408 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/047408
Bit line equalizer Feb 17, 2016 Issued
Array ( [id] => 11867273 [patent_doc_number] => 20170234558 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-08-17 [patent_title] => 'SYSTEM AND METHOD FOR HANDING OFF THE CONFIGURATION OF A BUILDING DEVICE FROM A CONTRACTOR TO A CUSTOMER USING A HANG TAG OR THE LIKE' [patent_app_type] => utility [patent_app_number] => 15/045149 [patent_app_country] => US [patent_app_date] => 2016-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 30 [patent_no_of_words] => 13058 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15045149 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/045149
System and method for handing off the configuration of a building device from a contractor to a customer using a hang tag or the like Feb 15, 2016 Issued
Array ( [id] => 16387431 [patent_doc_number] => 10812285 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-10-20 [patent_title] => Systems and methods for handing off configuration of a building device from a contractor to a customer [patent_app_type] => utility [patent_app_number] => 15/045120 [patent_app_country] => US [patent_app_date] => 2016-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 29 [patent_no_of_words] => 12780 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 342 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15045120 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/045120
Systems and methods for handing off configuration of a building device from a contractor to a customer Feb 15, 2016 Issued
Array ( [id] => 11867280 [patent_doc_number] => 20170234566 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-08-17 [patent_title] => 'MOBILE DEVICE WITH CONTRACTOR ACCESSIBLE SCREENS FOR CONFIGURING A BUILDING DEVICE' [patent_app_type] => utility [patent_app_number] => 15/045093 [patent_app_country] => US [patent_app_date] => 2016-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 30 [patent_no_of_words] => 13782 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15045093 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/045093
Mobile device with contractor accessible screens for configuring a building device Feb 15, 2016 Issued
Array ( [id] => 11194134 [patent_doc_number] => 09424952 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-08-23 [patent_title] => 'Circuits, methods, and media for detecting and countering aging degradation in memory cells' [patent_app_type] => utility [patent_app_number] => 15/018834 [patent_app_country] => US [patent_app_date] => 2016-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 5722 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 264 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15018834 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/018834
Circuits, methods, and media for detecting and countering aging degradation in memory cells Feb 7, 2016 Issued
Array ( [id] => 11466525 [patent_doc_number] => 09583163 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-02-28 [patent_title] => 'Loop structure for operations in memory' [patent_app_type] => utility [patent_app_number] => 15/013269 [patent_app_country] => US [patent_app_date] => 2016-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 41443 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15013269 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/013269
Loop structure for operations in memory Feb 1, 2016 Issued
Array ( [id] => 13893069 [patent_doc_number] => 10199086 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-02-05 [patent_title] => Semiconductor device having a reduced footprint of wires connecting a DLL circuit with an input/output buffer [patent_app_type] => utility [patent_app_number] => 15/011115 [patent_app_country] => US [patent_app_date] => 2016-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 9366 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15011115 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/011115
Semiconductor device having a reduced footprint of wires connecting a DLL circuit with an input/output buffer Jan 28, 2016 Issued
Array ( [id] => 11760079 [patent_doc_number] => 20170206948 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-07-20 [patent_title] => 'Encoded Global Bitlines for Memory and Other Circuits' [patent_app_type] => utility [patent_app_number] => 15/003279 [patent_app_country] => US [patent_app_date] => 2016-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4199 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15003279 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/003279
Encoded Global Bitlines for Memory and Other Circuits Jan 20, 2016 Abandoned
Array ( [id] => 11760078 [patent_doc_number] => 20170206947 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-07-20 [patent_title] => 'AUTOMATIC DELAY-LINE CALIBRATION USING A REPLICA ARRAY' [patent_app_type] => utility [patent_app_number] => 14/997901 [patent_app_country] => US [patent_app_date] => 2016-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 5732 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14997901 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/997901
Automatic delay-line calibration using a replica array Jan 17, 2016 Issued
Array ( [id] => 10787145 [patent_doc_number] => 20160133301 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-05-12 [patent_title] => 'MULTILAYERED SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 14/995067 [patent_app_country] => US [patent_app_date] => 2016-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 8743 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14995067 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/995067
Multilayered semiconductor device Jan 12, 2016 Issued
Array ( [id] => 11036017 [patent_doc_number] => 20160232973 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-08-11 [patent_title] => 'NONVOLATILE MEMORY AND STORAGE DEVICE INCLUDING NONVOLATILE MEMORY' [patent_app_type] => utility [patent_app_number] => 14/994173 [patent_app_country] => US [patent_app_date] => 2016-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 12891 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14994173 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/994173
Nonvolatile memory with block word line Jan 12, 2016 Issued
Array ( [id] => 11020894 [patent_doc_number] => 20160217848 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-07-28 [patent_title] => 'SEMICONDUCTOR DEVICE, ELECTRONIC COMPONENT, AND ELECTRONIC DEVICE' [patent_app_type] => utility [patent_app_number] => 14/993375 [patent_app_country] => US [patent_app_date] => 2016-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 22242 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14993375 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/993375
Semiconductor device, electronic component, and electronic device Jan 11, 2016 Issued
Array ( [id] => 11006903 [patent_doc_number] => 20160203855 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-07-14 [patent_title] => 'MEMORY DEVICE, RELATED METHOD, AND RELATED ELECTRONIC DEVICE' [patent_app_type] => utility [patent_app_number] => 14/986228 [patent_app_country] => US [patent_app_date] => 2015-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5308 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14986228 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/986228
MEMORY DEVICE, RELATED METHOD, AND RELATED ELECTRONIC DEVICE Dec 30, 2015 Abandoned
Array ( [id] => 13056627 [patent_doc_number] => 10049709 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-08-14 [patent_title] => Port modes for use with memory [patent_app_type] => utility [patent_app_number] => 14/986215 [patent_app_country] => US [patent_app_date] => 2015-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 10740 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 208 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14986215 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/986215
Port modes for use with memory Dec 30, 2015 Issued
Array ( [id] => 11681112 [patent_doc_number] => 09679646 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-06-13 [patent_title] => 'Nonvolatile semiconductor storage device and rewriting method thereof' [patent_app_type] => utility [patent_app_number] => 14/979739 [patent_app_country] => US [patent_app_date] => 2015-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 4792 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 206 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14979739 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/979739
Nonvolatile semiconductor storage device and rewriting method thereof Dec 27, 2015 Issued
Array ( [id] => 11564463 [patent_doc_number] => 09627055 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-04-18 [patent_title] => 'Phase change memory devices and systems having reduced voltage threshold drift and associated methods' [patent_app_type] => utility [patent_app_number] => 14/757831 [patent_app_country] => US [patent_app_date] => 2015-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 6373 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14757831 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/757831
Phase change memory devices and systems having reduced voltage threshold drift and associated methods Dec 25, 2015 Issued
Array ( [id] => 11564463 [patent_doc_number] => 09627055 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-04-18 [patent_title] => 'Phase change memory devices and systems having reduced voltage threshold drift and associated methods' [patent_app_type] => utility [patent_app_number] => 14/757831 [patent_app_country] => US [patent_app_date] => 2015-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 6373 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14757831 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/757831
Phase change memory devices and systems having reduced voltage threshold drift and associated methods Dec 25, 2015 Issued
Array ( [id] => 11564463 [patent_doc_number] => 09627055 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-04-18 [patent_title] => 'Phase change memory devices and systems having reduced voltage threshold drift and associated methods' [patent_app_type] => utility [patent_app_number] => 14/757831 [patent_app_country] => US [patent_app_date] => 2015-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 6373 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14757831 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/757831
Phase change memory devices and systems having reduced voltage threshold drift and associated methods Dec 25, 2015 Issued
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