Ronald Trice

Array ( [id] => 11494355 [patent_doc_number] => 20170068539 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-09 [patent_title] => 'HIGH PERFORMANCE ZERO BUBBLE CONDITIONAL BRANCH PREDICTION USING MICRO BRANCH TARGET BUFFER' [patent_app_type] => utility [patent_app_number] => 15/047617 [patent_app_country] => US [patent_app_date] => 2016-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 11157 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15047617 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11272545 [patent_doc_number] => 20160335092 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-11-17 [patent_title] => 'Using Very Long Instruction Word VLIW Cores In Many-Core Architectures' [patent_app_type] => utility [patent_app_number] => 15/046438 [patent_app_country] => US [patent_app_date] => 2016-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7579 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15046438 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11516246 [patent_doc_number] => 20170083320 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-23 [patent_title] => 'PREDICATED READ INSTRUCTIONS' [patent_app_type] => utility [patent_app_number] => 15/004761 [patent_app_country] => US [patent_app_date] => 2016-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 21364 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15004761 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14489323 [patent_doc_number] => 10331449 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-06-25 [patent_title] => Encoding instructions identifying first and second architectural register numbers [patent_app_type] => utility [patent_app_number] => 15/003828 [patent_app_country] => US [patent_app_date] => 2016-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 12077 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15003828 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15058843 [patent_doc_number] => 10459725 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-10-29 [patent_title] => Execution of load instructions in a processor [patent_app_type] => utility [patent_app_number] => 15/001628 [patent_app_country] => US [patent_app_date] => 2016-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5595 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15001628 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11731337 [patent_doc_number] => 20170192780 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-07-06 [patent_title] => 'Systems, Apparatuses, and Methods for Getting Even and Odd Data Elements' [patent_app_type] => utility [patent_app_number] => 14/984078 [patent_app_country] => US [patent_app_date] => 2015-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 16123 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14984078 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11731339 [patent_doc_number] => 20170192782 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-07-06 [patent_title] => 'Systems, Apparatuses, and Methods for Aggregate Gather and Stride' [patent_app_type] => utility [patent_app_number] => 14/984132 [patent_app_country] => US [patent_app_date] => 2015-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 18143 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14984132 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11731348 [patent_doc_number] => 20170192791 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-07-06 [patent_title] => 'Counter to Monitor Address Conflicts' [patent_app_type] => utility [patent_app_number] => 14/984115 [patent_app_country] => US [patent_app_date] => 2015-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 7983 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14984115 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11731338 [patent_doc_number] => 20170192781 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-07-06 [patent_title] => 'Systems, Apparatuses, and Methods for Strided Loads' [patent_app_type] => utility [patent_app_number] => 14/984124 [patent_app_country] => US [patent_app_date] => 2015-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 30 [patent_no_of_words] => 17670 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14984124 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11731340 [patent_doc_number] => 20170192783 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-07-06 [patent_title] => 'Systems, Apparatuses, and Methods for Stride Load' [patent_app_type] => utility [patent_app_number] => 14/984148 [patent_app_country] => US [patent_app_date] => 2015-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 15853 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14984148 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17106216 [patent_doc_number] => 11126433 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-09-21 [patent_title] => Block-based processor core composition register [patent_app_type] => utility [patent_app_number] => 14/757941 [patent_app_country] => US [patent_app_date] => 2015-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 27404 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 325 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14757941 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11516243 [patent_doc_number] => 20170083318 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-23 [patent_title] => 'Configuring modes of processor operation' [patent_app_type] => utility [patent_app_number] => 14/757944 [patent_app_country] => US [patent_app_date] => 2015-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 17413 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14757944 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11716913 [patent_doc_number] => 20170185412 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-29 [patent_title] => 'Processing devices to perform a key value lookup instruction' [patent_app_type] => utility [patent_app_number] => 14/757995 [patent_app_country] => US [patent_app_date] => 2015-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 16199 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14757995 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11716904 [patent_doc_number] => 20170185403 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-29 [patent_title] => 'Hardware content-associative data structure for acceleration of set operations' [patent_app_type] => utility [patent_app_number] => 14/757776 [patent_app_country] => US [patent_app_date] => 2015-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 38 [patent_figures_cnt] => 38 [patent_no_of_words] => 39804 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14757776 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11709044 [patent_doc_number] => 20170177543 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-22 [patent_title] => 'AGGREGATE SCATTER INSTRUCTIONS' [patent_app_type] => utility [patent_app_number] => 14/979047 [patent_app_country] => US [patent_app_date] => 2015-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 14408 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14979047 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11445142 [patent_doc_number] => 20170046163 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-02-16 [patent_title] => 'PROCESSOR INSTRUCTION SEQUENCE TRANSLATION' [patent_app_type] => utility [patent_app_number] => 14/868660 [patent_app_country] => US [patent_app_date] => 2015-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5522 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14868660 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11445135 [patent_doc_number] => 20170046156 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-02-16 [patent_title] => 'TABLE LOOKUP USING SIMD INSTRUCTIONS' [patent_app_type] => utility [patent_app_number] => 14/826199 [patent_app_country] => US [patent_app_date] => 2015-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5943 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14826199 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15106285 [patent_doc_number] => 10474467 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-11-12 [patent_title] => Processor instruction sequence translation [patent_app_type] => utility [patent_app_number] => 14/824410 [patent_app_country] => US [patent_app_date] => 2015-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 5424 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 223 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14824410 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11365985 [patent_doc_number] => 20170003966 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-01-05 [patent_title] => 'PROCESSOR WITH INSTRUCTION FOR INTERPOLATING TABLE LOOKUP VALUES' [patent_app_type] => utility [patent_app_number] => 14/788277 [patent_app_country] => US [patent_app_date] => 2015-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 11275 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14788277 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11314006 [patent_doc_number] => 20160350116 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-12-01 [patent_title] => 'MITIGATING WRONG-PATH EFFECTS IN BRANCH PREDICTION' [patent_app_type] => utility [patent_app_number] => 14/726450 [patent_app_country] => US [patent_app_date] => 2015-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 8805 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14726450 [rel_patent_id] =>[rel_patent_doc_number] =>)