Search

Ronald Trice

Examiner (ID: 17821)

Most Active Art Unit
2515
Art Unit(s)
2816, 2515, 2504
Total Applications
257
Issued Applications
188
Pending Applications
7
Abandoned Applications
62

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17794220 [patent_doc_number] => 20220253312 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-08-11 [patent_title] => DYNAMIC ALLOCATION OF EXECUTABLE CODE FOR MULTI-ARCHITECTURE HETEROGENEOUS COMPUTING [patent_app_type] => utility [patent_app_number] => 17/406151 [patent_app_country] => US [patent_app_date] => 2021-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9232 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17406151 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/406151
Dynamic allocation of executable code for multiarchitecture heterogeneous computing Aug 18, 2021 Issued
Array ( [id] => 18839381 [patent_doc_number] => 11847455 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-12-19 [patent_title] => Clearing register data using a write enable signal [patent_app_type] => utility [patent_app_number] => 17/345186 [patent_app_country] => US [patent_app_date] => 2021-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4352 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17345186 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/345186
Clearing register data using a write enable signal Jun 10, 2021 Issued
Array ( [id] => 18218172 [patent_doc_number] => 11593109 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-02-28 [patent_title] => Sharing instruction cache lines between multiple threads [patent_app_type] => utility [patent_app_number] => 17/341209 [patent_app_country] => US [patent_app_date] => 2021-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 4 [patent_no_of_words] => 8259 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17341209 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/341209
Sharing instruction cache lines between multiple threads Jun 6, 2021 Issued
Array ( [id] => 18218171 [patent_doc_number] => 11593108 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-02-28 [patent_title] => Sharing instruction cache footprint between multiple threads [patent_app_type] => utility [patent_app_number] => 17/341192 [patent_app_country] => US [patent_app_date] => 2021-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 10056 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17341192 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/341192
Sharing instruction cache footprint between multiple threads Jun 6, 2021 Issued
Array ( [id] => 19719368 [patent_doc_number] => 12204907 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-01-21 [patent_title] => Processor supporting position-independent addressing [patent_app_type] => utility [patent_app_number] => 17/335945 [patent_app_country] => US [patent_app_date] => 2021-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 7213 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17335945 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/335945
Processor supporting position-independent addressing May 31, 2021 Issued
Array ( [id] => 18038331 [patent_doc_number] => 20220382547 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-01 [patent_title] => MICROPROCESSOR AND METHOD FOR ISSUING LOAD/STORE INSTRUCTION [patent_app_type] => utility [patent_app_number] => 17/329181 [patent_app_country] => US [patent_app_date] => 2021-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18505 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17329181 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/329181
Microprocessor and method for speculatively issuing load/store instruction with non-deterministic access time using scoreboard May 24, 2021 Issued
Array ( [id] => 17230670 [patent_doc_number] => 20210357227 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-11-18 [patent_title] => RISC-V ISA BASED MICRO-CONTROLLER UNIT FOR LOW POWER IOT AND EDGE COMPUTING APPLICATIONS [patent_app_type] => utility [patent_app_number] => 17/317862 [patent_app_country] => US [patent_app_date] => 2021-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10008 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17317862 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/317862
RISC-V ISA BASED MICRO-CONTROLLER UNIT FOR LOW POWER IOT AND EDGE COMPUTING APPLICATIONS May 10, 2021 Abandoned
Array ( [id] => 18651543 [patent_doc_number] => 20230297379 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-21 [patent_title] => DATA PROCESSING APPARATUS AND RELATED PRODUCT [patent_app_type] => utility [patent_app_number] => 17/620527 [patent_app_country] => US [patent_app_date] => 2021-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13856 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17620527 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/620527
Data processing apparatus and related product Apr 27, 2021 Issued
Array ( [id] => 18229833 [patent_doc_number] => 20230068827 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-02 [patent_title] => DATA PROCESSING METHOD AND DEVICE, AND RELATED PRODUCT [patent_app_type] => utility [patent_app_number] => 17/620516 [patent_app_country] => US [patent_app_date] => 2021-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8488 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17620516 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/620516
DATA PROCESSING METHOD AND DEVICE, AND RELATED PRODUCT Apr 27, 2021 Pending
Array ( [id] => 17962091 [patent_doc_number] => 20220342672 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-27 [patent_title] => RESCHEDULING A LOAD INSTRUCTION BASED ON PAST REPLAYS [patent_app_type] => utility [patent_app_number] => 17/241726 [patent_app_country] => US [patent_app_date] => 2021-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2670 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17241726 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/241726
Rescheduling a load instruction based on past replays Apr 26, 2021 Issued
Array ( [id] => 17024109 [patent_doc_number] => 20210247980 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-08-12 [patent_title] => MECHANISM FOR INTERRUPTING AND RESUMING EXECUTION ON AN UNPROTECTED PIPELINE PROCESSOR [patent_app_type] => utility [patent_app_number] => 17/241198 [patent_app_country] => US [patent_app_date] => 2021-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11222 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17241198 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/241198
Mechanism for interrupting and resuming execution on an unprotected pipeline processor Apr 26, 2021 Issued
Array ( [id] => 16993982 [patent_doc_number] => 20210232402 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-29 [patent_title] => METHOD FOR VECTORIZING HEAPSORT USING HORIZONTAL AGGREGATION SIMD INSTRUCTIONS [patent_app_type] => utility [patent_app_number] => 17/227167 [patent_app_country] => US [patent_app_date] => 2021-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10244 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 241 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17227167 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/227167
Method for vectorizing heapsort using horizontal aggregation SIMD instructions Apr 8, 2021 Issued
Array ( [id] => 16964817 [patent_doc_number] => 20210216316 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-15 [patent_title] => IMPLIED FENCE ON STREAM OPEN [patent_app_type] => utility [patent_app_number] => 17/216821 [patent_app_country] => US [patent_app_date] => 2021-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9910 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17216821 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/216821
Implied fence on stream open Mar 29, 2021 Issued
Array ( [id] => 18966347 [patent_doc_number] => 11900117 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-02-13 [patent_title] => Mechanism to queue multiple streams to run on streaming engine [patent_app_type] => utility [patent_app_number] => 17/213509 [patent_app_country] => US [patent_app_date] => 2021-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 37 [patent_no_of_words] => 29761 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17213509 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/213509
Mechanism to queue multiple streams to run on streaming engine Mar 25, 2021 Issued
Array ( [id] => 17076661 [patent_doc_number] => 11113059 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-09-07 [patent_title] => Dynamic allocation of executable code for multi-architecture heterogeneous computing [patent_app_type] => utility [patent_app_number] => 17/172134 [patent_app_country] => US [patent_app_date] => 2021-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 9201 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17172134 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/172134
Dynamic allocation of executable code for multi-architecture heterogeneous computing Feb 9, 2021 Issued
Array ( [id] => 16950298 [patent_doc_number] => 20210208990 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-08 [patent_title] => APPARATUS AND METHOD FOR GENERATING PERFORMANCE MONITORING METRICS [patent_app_type] => utility [patent_app_number] => 17/125694 [patent_app_country] => US [patent_app_date] => 2020-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16536 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17125694 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/125694
APPARATUS AND METHOD FOR GENERATING PERFORMANCE MONITORING METRICS Dec 16, 2020 Abandoned
Array ( [id] => 16623469 [patent_doc_number] => 20210042122 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-02-11 [patent_title] => METHOD FOR EXECUTING INSTRUCTIONS IN CPU [patent_app_type] => utility [patent_app_number] => 17/082509 [patent_app_country] => US [patent_app_date] => 2020-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6097 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17082509 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/082509
Method for replenishing a thread queue with a target instruction of a jump instruction Oct 27, 2020 Issued
Array ( [id] => 18810729 [patent_doc_number] => 20230385065 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-30 [patent_title] => Apparatus and Method for Simultaneous Multithreaded Instruction Scheduling in a Microprocessor [patent_app_type] => utility [patent_app_number] => 18/031070 [patent_app_country] => US [patent_app_date] => 2020-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8458 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -24 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18031070 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/031070
Apparatus and Method for Simultaneous Multithreaded Instruction Scheduling in a Microprocessor Oct 13, 2020 Pending
Array ( [id] => 17157826 [patent_doc_number] => 20210318877 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-10-14 [patent_title] => MICROPROCESSOR WITH INSTRUCTION FETCHING FAILURE SOLUTION [patent_app_type] => utility [patent_app_number] => 17/069191 [patent_app_country] => US [patent_app_date] => 2020-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15199 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17069191 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/069191
Microprocessor with instruction fetching failure solution Oct 12, 2020 Issued
Array ( [id] => 20079812 [patent_doc_number] => 12353881 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-08 [patent_title] => Circuitry and methods for power efficient generation of length markers for a variable length instruction set [patent_app_type] => utility [patent_app_number] => 17/033680 [patent_app_country] => US [patent_app_date] => 2020-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 24 [patent_no_of_words] => 15972 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 204 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17033680 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/033680
Circuitry and methods for power efficient generation of length markers for a variable length instruction set Sep 25, 2020 Issued
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