Ronnie Kirby Jordan

Array ( [id] => 17598109 [patent_doc_number] => 20220147683 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-12 [patent_title] => Method for implementing an integrated circuit comprising a random-access memory-in-logic [patent_app_type] => utility [patent_app_number] => 17/438795 [patent_app_country] => US [patent_app_date] => 2020-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5903 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 28 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17438795 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16758858 [patent_doc_number] => 10977410 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-04-13 [patent_title] => IC routing for silicon circuits with smaller geometries [patent_app_type] => utility [patent_app_number] => 16/810624 [patent_app_country] => US [patent_app_date] => 2020-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6960 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16810624 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18387555 [patent_doc_number] => 11658350 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-05-23 [patent_title] => Smart battery management systems [patent_app_type] => utility [patent_app_number] => 16/803127 [patent_app_country] => US [patent_app_date] => 2020-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 17531 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16803127 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16272886 [patent_doc_number] => 20200274374 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-08-27 [patent_title] => DETECTION CIRCUIT AND METHOD [patent_app_type] => utility [patent_app_number] => 16/799729 [patent_app_country] => US [patent_app_date] => 2020-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12759 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 358 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16799729 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16082065 [patent_doc_number] => 20200195019 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-06-18 [patent_title] => ELECTRONIC DEVICE, METHOD OF CONTROLLING CHARGING BY ELECTRONIC DEVICE, AND METHOD OF SUPPLYING POWER BY POWER SUPPLY DEVICE [patent_app_type] => utility [patent_app_number] => 16/797688 [patent_app_country] => US [patent_app_date] => 2020-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17309 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16797688 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17325593 [patent_doc_number] => 11216607 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-01-04 [patent_title] => Double glitch capture mode power integrity analysis [patent_app_type] => utility [patent_app_number] => 16/793981 [patent_app_country] => US [patent_app_date] => 2020-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 4189 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16793981 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17559624 [patent_doc_number] => 11316350 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-04-26 [patent_title] => Battery management apparatus and operating method thereof, and battery management system [patent_app_type] => utility [patent_app_number] => 16/789604 [patent_app_country] => US [patent_app_date] => 2020-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 15 [patent_no_of_words] => 8811 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16789604 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17545795 [patent_doc_number] => 11310946 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-04-19 [patent_title] => Automotive wireless charger with self temperature management [patent_app_type] => utility [patent_app_number] => 16/788162 [patent_app_country] => US [patent_app_date] => 2020-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 7883 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16788162 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16478599 [patent_doc_number] => 10853548 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-12-01 [patent_title] => Reconfiguration of hardware components of an integrated circuit [patent_app_type] => utility [patent_app_number] => 16/788157 [patent_app_country] => US [patent_app_date] => 2020-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 11747 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16788157 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18310470 [patent_doc_number] => 20230114370 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-13 [patent_title] => SHORT-DEPTH ACTIVE LEARNING QUANTUM AMPLITUDE ESTIMATION WITHOUT EIGENSTATE COLLAPSE [patent_app_type] => utility [patent_app_number] => 16/778878 [patent_app_country] => US [patent_app_date] => 2020-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15234 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16778878 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16225248 [patent_doc_number] => 20200250365 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-08-06 [patent_title] => TRANSISTOR SIZING FOR PARAMETER OBFUSCATION OF ANALOG CIRCUITS [patent_app_type] => utility [patent_app_number] => 16/778550 [patent_app_country] => US [patent_app_date] => 2020-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3672 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -1 [patent_words_short_claim] => 36 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16778550 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16788298 [patent_doc_number] => 10990732 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-04-27 [patent_title] => System frequency margin recovery via distributed critical path monitors (CPM) [patent_app_type] => utility [patent_app_number] => 16/777443 [patent_app_country] => US [patent_app_date] => 2020-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 7229 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16777443 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15967089 [patent_doc_number] => 20200167296 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-05-28 [patent_title] => SYSTEM AND METHOD FOR ROUTING BUS INCLUDING BUFFER [patent_app_type] => utility [patent_app_number] => 16/776755 [patent_app_country] => US [patent_app_date] => 2020-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10082 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16776755 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16478594 [patent_doc_number] => 10853543 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-12-01 [patent_title] => Logical detection of electronic circuit power sequence risks [patent_app_type] => utility [patent_app_number] => 16/776118 [patent_app_country] => US [patent_app_date] => 2020-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 12037 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 242 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16776118 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18781124 [patent_doc_number] => 11822866 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-11-21 [patent_title] => Computer-assisted method for determining a microfluidic circuit architecture reproducing a neuronal circuit [patent_app_type] => utility [patent_app_number] => 17/429502 [patent_app_country] => US [patent_app_date] => 2020-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 4993 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 257 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17429502 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16895350 [patent_doc_number] => 11036906 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-06-15 [patent_title] => Method and apparatus to accelerate verification signoff by selective re-use of integrated coverage models [patent_app_type] => utility [patent_app_number] => 16/751623 [patent_app_country] => US [patent_app_date] => 2020-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 6704 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16751623 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16501717 [patent_doc_number] => 10867106 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-12-15 [patent_title] => Routing for length-matched nets in interposer designs [patent_app_type] => utility [patent_app_number] => 16/749807 [patent_app_country] => US [patent_app_date] => 2020-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 8633 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 253 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16749807 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18607074 [patent_doc_number] => 11748542 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-09-05 [patent_title] => Systems and methods for integrated circuit layout [patent_app_type] => utility [patent_app_number] => 16/746029 [patent_app_country] => US [patent_app_date] => 2020-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 10505 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16746029 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15907473 [patent_doc_number] => 20200153257 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-05-14 [patent_title] => APPARATUSES AND METHODS FOR REMOVING DEFECTIVE ENERGY STORAGE CELLS FROM AN ENERGY STORAGE ARRAY [patent_app_type] => utility [patent_app_number] => 16/745284 [patent_app_country] => US [patent_app_date] => 2020-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3936 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16745284 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17562572 [patent_doc_number] => 20220126721 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-28 [patent_title] => METHOD FOR OPERATING A CHARGING STATION FOR VEHICLES [patent_app_type] => utility [patent_app_number] => 17/422738 [patent_app_country] => US [patent_app_date] => 2020-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2956 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 24 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17422738 [rel_patent_id] =>[rel_patent_doc_number] =>)