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Ronnie Kirby Jordan

Examiner (ID: 4379)

Most Active Art Unit
1747
Art Unit(s)
1747, 4146
Total Applications
116
Issued Applications
43
Pending Applications
52
Abandoned Applications
21

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 15504615 [patent_doc_number] => 20200052496 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-02-13 [patent_title] => MOTHERBOARD WITH A SMART CHARGING FUNCTION [patent_app_type] => utility [patent_app_number] => 16/356515 [patent_app_country] => US [patent_app_date] => 2019-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5579 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 265 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16356515 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/356515
Motherboard with a smart charging function Mar 17, 2019 Issued
Array ( [id] => 18668823 [patent_doc_number] => 11775727 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-03 [patent_title] => Method for generating layout diagram including wiring arrangement [patent_app_type] => utility [patent_app_number] => 16/299973 [patent_app_country] => US [patent_app_date] => 2019-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 16 [patent_no_of_words] => 17751 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16299973 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/299973
Method for generating layout diagram including wiring arrangement Mar 11, 2019 Issued
Array ( [id] => 17507843 [patent_doc_number] => 20220100946 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-31 [patent_title] => ELECTRICAL DESIGN RULE CHECKING METHOD AND DEVICE FOR INTEGRATED CIRCUIT [patent_app_type] => utility [patent_app_number] => 17/426612 [patent_app_country] => US [patent_app_date] => 2019-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2417 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17426612 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/426612
ELECTRICAL DESIGN RULE CHECKING METHOD AND DEVICE FOR INTEGRATED CIRCUIT Mar 4, 2019 Pending
Array ( [id] => 16454287 [patent_doc_number] => 20200363713 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-11-19 [patent_title] => BINARIZATION METHOD AND FREEFORM MASK OPTIMIZATION FLOW [patent_app_type] => utility [patent_app_number] => 16/967789 [patent_app_country] => US [patent_app_date] => 2019-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12614 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16967789 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/967789
Binarization method and freeform mask optimization flow Feb 14, 2019 Issued
Array ( [id] => 16447200 [patent_doc_number] => 10839129 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-11-17 [patent_title] => Characterization of spatial correlation in integrated circuit development [patent_app_type] => utility [patent_app_number] => 16/274522 [patent_app_country] => US [patent_app_date] => 2019-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6276 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 238 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16274522 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/274522
Characterization of spatial correlation in integrated circuit development Feb 12, 2019 Issued
Array ( [id] => 14720327 [patent_doc_number] => 20190251227 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-08-15 [patent_title] => AUTOMATED NETWORK-ON-CHIP DESIGN [patent_app_type] => utility [patent_app_number] => 16/274173 [patent_app_country] => US [patent_app_date] => 2019-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7017 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16274173 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/274173
Automated network-on-chip design Feb 11, 2019 Issued
Array ( [id] => 16371454 [patent_doc_number] => 10803216 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-10-13 [patent_title] => Combinational logic circuit optimization [patent_app_type] => utility [patent_app_number] => 16/272701 [patent_app_country] => US [patent_app_date] => 2019-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 5779 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16272701 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/272701
Combinational logic circuit optimization Feb 10, 2019 Issued
Array ( [id] => 14405559 [patent_doc_number] => 20190168623 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-06-06 [patent_title] => Electric Vehicles and Charging Stations [patent_app_type] => utility [patent_app_number] => 16/266175 [patent_app_country] => US [patent_app_date] => 2019-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15464 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16266175 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/266175
Charging stations for electric vehicles Feb 3, 2019 Issued
Array ( [id] => 14348011 [patent_doc_number] => 20190155978 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-23 [patent_title] => Computer Implemented System and Method for Generating a Layout of a Cell Defining a Circuit Component [patent_app_type] => utility [patent_app_number] => 16/253075 [patent_app_country] => US [patent_app_date] => 2019-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10450 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -24 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16253075 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/253075
Computer implemented system and method for generating a layout of a cell defining a circuit component Jan 20, 2019 Issued
Array ( [id] => 14314837 [patent_doc_number] => 20190147122 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-16 [patent_title] => VERIFICATION OF HARDWARE DESIGNS TO IMPLEMENT FLOATING POINT POWER FUNCTIONS [patent_app_type] => utility [patent_app_number] => 16/249834 [patent_app_country] => US [patent_app_date] => 2019-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15354 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16249834 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/249834
Verification of hardware designs to implement floating point power functions Jan 15, 2019 Issued
Array ( [id] => 14655517 [patent_doc_number] => 20190234887 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-08-01 [patent_title] => METHOD OF EXAMINING LOCATIONS IN A WAFER WITH ADJUSTABLE NAVIGATION ACCURACY AND SYSTEM THEREOF [patent_app_type] => utility [patent_app_number] => 16/227453 [patent_app_country] => US [patent_app_date] => 2018-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10680 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16227453 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/227453
Method of examining locations in a wafer with adjustable navigation accuracy and system thereof Dec 19, 2018 Issued
Array ( [id] => 14189357 [patent_doc_number] => 20190114384 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-04-18 [patent_title] => VERIFICATION OF PHOTONIC INTEGRATED CIRCUITS [patent_app_type] => utility [patent_app_number] => 16/217956 [patent_app_country] => US [patent_app_date] => 2018-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5485 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16217956 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/217956
Verification of photonic integrated circuits Dec 11, 2018 Issued
Array ( [id] => 16201023 [patent_doc_number] => 10726190 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-07-28 [patent_title] => Systems and methods for identifying wires for adjustment [patent_app_type] => utility [patent_app_number] => 16/216682 [patent_app_country] => US [patent_app_date] => 2018-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 3957 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16216682 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/216682
Systems and methods for identifying wires for adjustment Dec 10, 2018 Issued
Array ( [id] => 15526227 [patent_doc_number] => 20200055419 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-02-20 [patent_title] => ELECTRIC VEHICLE RESERVATION CHARGING SYSTEM AND METHOD [patent_app_type] => utility [patent_app_number] => 16/213371 [patent_app_country] => US [patent_app_date] => 2018-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7964 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16213371 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/213371
Electric vehicle reservation charging system and method Dec 6, 2018 Issued
Array ( [id] => 16575216 [patent_doc_number] => 10897146 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-01-19 [patent_title] => Battery protection integrated circuit and battery management system [patent_app_type] => utility [patent_app_number] => 16/211937 [patent_app_country] => US [patent_app_date] => 2018-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6262 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 251 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16211937 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/211937
Battery protection integrated circuit and battery management system Dec 5, 2018 Issued
Array ( [id] => 16022181 [patent_doc_number] => 20200185934 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-06-11 [patent_title] => ENERGY STORAGE DEVICE CHARGE BALANCING [patent_app_type] => utility [patent_app_number] => 16/211328 [patent_app_country] => US [patent_app_date] => 2018-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7215 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16211328 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/211328
Energy storage device charge balancing Dec 5, 2018 Issued
Array ( [id] => 18493594 [patent_doc_number] => 11699012 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-07-11 [patent_title] => Coverage based microelectronic circuit, and method for providing a design of a microelectronic circuit [patent_app_type] => utility [patent_app_number] => 17/297623 [patent_app_country] => US [patent_app_date] => 2018-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 9518 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17297623 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/297623
Coverage based microelectronic circuit, and method for providing a design of a microelectronic circuit Nov 26, 2018 Issued
Array ( [id] => 14157815 [patent_doc_number] => 20190106010 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-04-11 [patent_title] => Method and Apparatus for a Wireless Charging System [patent_app_type] => utility [patent_app_number] => 16/198118 [patent_app_country] => US [patent_app_date] => 2018-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8703 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16198118 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/198118
Method and apparatus for a wireless charging system Nov 20, 2018 Issued
Array ( [id] => 16216695 [patent_doc_number] => 10732499 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-08-04 [patent_title] => Method and system for cross-tile OPC consistency [patent_app_type] => utility [patent_app_number] => 16/195953 [patent_app_country] => US [patent_app_date] => 2018-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 7586 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 264 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16195953 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/195953
Method and system for cross-tile OPC consistency Nov 19, 2018 Issued
Array ( [id] => 16371462 [patent_doc_number] => 10803224 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-10-13 [patent_title] => Propagating constants of structured soft blocks while preserving the relative placement structure [patent_app_type] => utility [patent_app_number] => 16/194381 [patent_app_country] => US [patent_app_date] => 2018-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 11068 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16194381 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/194381
Propagating constants of structured soft blocks while preserving the relative placement structure Nov 17, 2018 Issued
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