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Ronnie Kirby Jordan

Examiner (ID: 4379)

Most Active Art Unit
1747
Art Unit(s)
1747, 4146
Total Applications
116
Issued Applications
43
Pending Applications
52
Abandoned Applications
21

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18607080 [patent_doc_number] => 11748548 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-09-05 [patent_title] => Hierarchical clock tree implementation [patent_app_type] => utility [patent_app_number] => 17/573632 [patent_app_country] => US [patent_app_date] => 2022-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 7251 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17573632 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/573632
Hierarchical clock tree implementation Jan 10, 2022 Issued
Array ( [id] => 18819868 [patent_doc_number] => 20230394208 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-07 [patent_title] => DEVICE VERIFICATION METHOD, UVM VERIFICATION PLATFORM, ELECTRONIC APPARATUS AND STORAGE MEDIUM [patent_app_type] => utility [patent_app_number] => 18/259691 [patent_app_country] => US [patent_app_date] => 2021-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5248 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18259691 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/259691
Device verification method, UVM verification platform, electronic apparatus and storage medium Oct 28, 2021 Issued
Array ( [id] => 17535706 [patent_doc_number] => 20220114315 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-14 [patent_title] => VERIFICATION OF HARDWARE DESIGN FOR COMPONENT THAT EVALUATES AN ALGEBRAIC EXPRESSION USING DECOMPOSITION AND RECOMBINATION [patent_app_type] => utility [patent_app_number] => 17/501219 [patent_app_country] => US [patent_app_date] => 2021-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19098 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17501219 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/501219
Verification of hardware design for component that evaluates an algebraic expression using decomposition and recombination Oct 13, 2021 Issued
Array ( [id] => 18310958 [patent_doc_number] => 20230114858 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-13 [patent_title] => CIRCUIT DESIGN SIMULATION AND CLOCK EVENT REDUCTION [patent_app_type] => utility [patent_app_number] => 17/496198 [patent_app_country] => US [patent_app_date] => 2021-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8964 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17496198 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/496198
CIRCUIT DESIGN SIMULATION AND CLOCK EVENT REDUCTION Oct 6, 2021 Pending
Array ( [id] => 17558204 [patent_doc_number] => 11314913 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-04-26 [patent_title] => Information processing apparatus, program, and simulation method [patent_app_type] => utility [patent_app_number] => 17/482924 [patent_app_country] => US [patent_app_date] => 2021-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 18 [patent_no_of_words] => 4859 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17482924 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/482924
Information processing apparatus, program, and simulation method Sep 22, 2021 Issued
Array ( [id] => 17508062 [patent_doc_number] => 20220101165 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-31 [patent_title] => CONTROLLABLE QUANTUM LOGIC GATES WITH MEASUREMENT AND METHODS FOR USE THEREWITH [patent_app_type] => utility [patent_app_number] => 17/447848 [patent_app_country] => US [patent_app_date] => 2021-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10677 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17447848 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/447848
Controllable quantum logic gates with measurement and methods for use therewith Sep 15, 2021 Issued
Array ( [id] => 18211565 [patent_doc_number] => 20230057828 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-02-23 [patent_title] => BALANCING CYCLE STEALING WITH EARLY MODE VIOLATIONS [patent_app_type] => utility [patent_app_number] => 17/407510 [patent_app_country] => US [patent_app_date] => 2021-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9851 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17407510 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/407510
Balancing cycle stealing with early mode violations Aug 19, 2021 Issued
Array ( [id] => 18268078 [patent_doc_number] => 20230089320 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-23 [patent_title] => LOGICAL NODE LAYOUT METHOD AND APPARATUS, COMPUTER DEVICE, AND STORAGE MEDIUM [patent_app_type] => utility [patent_app_number] => 17/909417 [patent_app_country] => US [patent_app_date] => 2021-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10631 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17909417 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/909417
Logical node layout method and apparatus, computer device, and storage medium Aug 16, 2021 Issued
Array ( [id] => 17690823 [patent_doc_number] => 20220198116 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-23 [patent_title] => METHOD AND SYSTEM FOR LOGIC DESIGN PARTITIONING [patent_app_type] => utility [patent_app_number] => 17/402632 [patent_app_country] => US [patent_app_date] => 2021-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3709 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 237 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17402632 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/402632
Method and system for logic design partitioning Aug 15, 2021 Issued
Array ( [id] => 18720391 [patent_doc_number] => 11797737 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-24 [patent_title] => Finding equivalent classes of hard defects in stacked MOSFET arrays [patent_app_type] => utility [patent_app_number] => 17/400360 [patent_app_country] => US [patent_app_date] => 2021-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 11837 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17400360 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/400360
Finding equivalent classes of hard defects in stacked MOSFET arrays Aug 11, 2021 Issued
Array ( [id] => 17413291 [patent_doc_number] => 20220048195 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-02-17 [patent_title] => System and Methods for Providing Battery Charging Service to Parked Electric Vehicles [patent_app_type] => utility [patent_app_number] => 17/397861 [patent_app_country] => US [patent_app_date] => 2021-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7049 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17397861 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/397861
System and Methods for Providing Battery Charging Service to Parked Electric Vehicles Aug 8, 2021 Pending
Array ( [id] => 18177670 [patent_doc_number] => 20230038399 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-02-09 [patent_title] => NOISE IMPACT ON FUNCTION (NIOF) REDUCTION FOR INTEGRATED CIRCUIT DESIGN [patent_app_type] => utility [patent_app_number] => 17/397197 [patent_app_country] => US [patent_app_date] => 2021-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6767 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 46 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17397197 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/397197
Noise impact on function (NIOF) reduction for integrated circuit design Aug 8, 2021 Issued
Array ( [id] => 18177592 [patent_doc_number] => 20230038321 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-02-09 [patent_title] => REGION-BASED LAYOUT ROUTING [patent_app_type] => utility [patent_app_number] => 17/395951 [patent_app_country] => US [patent_app_date] => 2021-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6159 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17395951 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/395951
Region-based layout routing Aug 5, 2021 Issued
Array ( [id] => 18839322 [patent_doc_number] => 11847396 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-12-19 [patent_title] => Integrated circuit design using multi-bit combinational cells [patent_app_type] => utility [patent_app_number] => 17/393869 [patent_app_country] => US [patent_app_date] => 2021-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 12152 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17393869 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/393869
Integrated circuit design using multi-bit combinational cells Aug 3, 2021 Issued
Array ( [id] => 18548627 [patent_doc_number] => 11721990 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-08 [patent_title] => Power tool system having wireless communicator [patent_app_type] => utility [patent_app_number] => 17/393780 [patent_app_country] => US [patent_app_date] => 2021-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 39 [patent_figures_cnt] => 47 [patent_no_of_words] => 30115 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17393780 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/393780
Power tool system having wireless communicator Aug 3, 2021 Issued
Array ( [id] => 18183279 [patent_doc_number] => 20230044009 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-02-09 [patent_title] => VEHICLE ELECTRICAL SYSTEM [patent_app_type] => utility [patent_app_number] => 17/392597 [patent_app_country] => US [patent_app_date] => 2021-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7923 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17392597 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/392597
VEHICLE ELECTRICAL SYSTEM Aug 2, 2021 Pending
Array ( [id] => 17690822 [patent_doc_number] => 20220198115 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-23 [patent_title] => MODULAR PERIPHERY TILE FOR INTEGRATED CIRCUIT DEVICE [patent_app_type] => utility [patent_app_number] => 17/392218 [patent_app_country] => US [patent_app_date] => 2021-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4693 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17392218 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/392218
Modular periphery tile for integrated circuit device Aug 1, 2021 Issued
Array ( [id] => 19167568 [patent_doc_number] => 11983476 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-05-14 [patent_title] => Technology-independent line end routing [patent_app_type] => utility [patent_app_number] => 17/389931 [patent_app_country] => US [patent_app_date] => 2021-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 27 [patent_no_of_words] => 15956 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17389931 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/389931
Technology-independent line end routing Jul 29, 2021 Issued
Array ( [id] => 18506630 [patent_doc_number] => 11704448 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-07-18 [patent_title] => Computer implemented system and method of translation of verification commands of an electronic design [patent_app_type] => utility [patent_app_number] => 17/385505 [patent_app_country] => US [patent_app_date] => 2021-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 13028 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 385 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17385505 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/385505
Computer implemented system and method of translation of verification commands of an electronic design Jul 25, 2021 Issued
Array ( [id] => 17216719 [patent_doc_number] => 20210350057 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-11-11 [patent_title] => VERIFICATION OF HARDWARE DESIGN FOR INTEGRATED CIRCUIT IMPLEMENTING POLYNOMIAL INPUT VARIABLE FUNCTION [patent_app_type] => utility [patent_app_number] => 17/384483 [patent_app_country] => US [patent_app_date] => 2021-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 23556 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17384483 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/384483
Verification of hardware design for integrated circuit implementing polynomial input variable function Jul 22, 2021 Issued
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