![](/images/general/no_picture/200_user.png)
Ronnie Kirby Jordan
Examiner (ID: 4379)
Most Active Art Unit | 1747 |
Art Unit(s) | 1747, 4146 |
Total Applications | 116 |
Issued Applications | 43 |
Pending Applications | 52 |
Abandoned Applications | 21 |
Applications
Application number | Title of the application | Filing Date | Status |
---|---|---|---|
Array
(
[id] => 18951405
[patent_doc_number] => 11894713
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-02-06
[patent_title] => Power supply circuit providing control over adaptive charging and charging capability, power supply unit thereof, and charging control method thereof
[patent_app_type] => utility
[patent_app_number] => 17/200884
[patent_app_country] => US
[patent_app_date] => 2021-03-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 6547
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 308
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17200884
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/200884 | Power supply circuit providing control over adaptive charging and charging capability, power supply unit thereof, and charging control method thereof | Mar 13, 2021 | Issued |
Array
(
[id] => 17622249
[patent_doc_number] => 11341306
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2022-05-24
[patent_title] => Method for building spice circuit model of an optical coupler
[patent_app_type] => utility
[patent_app_number] => 17/199450
[patent_app_country] => US
[patent_app_date] => 2021-03-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 8
[patent_no_of_words] => 6210
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 384
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17199450
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/199450 | Method for building spice circuit model of an optical coupler | Mar 11, 2021 | Issued |
Array
(
[id] => 17232987
[patent_doc_number] => 20210359544
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-11-18
[patent_title] => WIRELESS POWER TRANSFER IN MODULAR SYSTEMS
[patent_app_type] => utility
[patent_app_number] => 17/198978
[patent_app_country] => US
[patent_app_date] => 2021-03-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7458
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -23
[patent_words_short_claim] => 82
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17198978
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/198978 | WIRELESS POWER TRANSFER IN MODULAR SYSTEMS | Mar 10, 2021 | Pending |
Array
(
[id] => 17346070
[patent_doc_number] => 20220012401
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-01-13
[patent_title] => METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SYSTEM FOR SAME
[patent_app_type] => utility
[patent_app_number] => 17/199023
[patent_app_country] => US
[patent_app_date] => 2021-03-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 17078
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -15
[patent_words_short_claim] => 56
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17199023
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/199023 | Method of manufacturing semiconductor device and system for same | Mar 10, 2021 | Issued |
Array
(
[id] => 17231004
[patent_doc_number] => 20210357561
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-11-18
[patent_title] => SYSTEMS AND METHODS FOR INTEGRATED CIRCUIT LAYOUT
[patent_app_type] => utility
[patent_app_number] => 17/195953
[patent_app_country] => US
[patent_app_date] => 2021-03-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 16677
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 79
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17195953
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/195953 | Systems and methods for integrated circuit layout | Mar 8, 2021 | Issued |
Array
(
[id] => 18782594
[patent_doc_number] => 11824365
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-11-21
[patent_title] => Portable blender with wireless charging
[patent_app_type] => utility
[patent_app_number] => 17/195338
[patent_app_country] => US
[patent_app_date] => 2021-03-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 7
[patent_no_of_words] => 8804
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 544
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17195338
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/195338 | Portable blender with wireless charging | Mar 7, 2021 | Issued |
Array
(
[id] => 17476215
[patent_doc_number] => 20220083719
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-03-17
[patent_title] => LOGIC SIMULATION VERIFICATION SYSTEM, LOGIC SIMULATION VERIFICATION METHOD, AND PROGRAM
[patent_app_type] => utility
[patent_app_number] => 17/190097
[patent_app_country] => US
[patent_app_date] => 2021-03-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9008
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -9
[patent_words_short_claim] => 209
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17190097
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/190097 | Logic simulation verification system, logic simulation verification method, and program | Mar 1, 2021 | Issued |
Array
(
[id] => 17839817
[patent_doc_number] => 20220277122
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-09-01
[patent_title] => Soft Error-Mitigating Semiconductor Design System and Associated Methods
[patent_app_type] => utility
[patent_app_number] => 17/187516
[patent_app_country] => US
[patent_app_date] => 2021-02-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6776
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -1
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17187516
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/187516 | Soft error-mitigating semiconductor design system and associated methods | Feb 25, 2021 | Issued |
Array
(
[id] => 18668808
[patent_doc_number] => 11775712
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2023-10-03
[patent_title] => Determining mechanical reliability of electronic packages assembled with thermal pads
[patent_app_type] => utility
[patent_app_number] => 17/179767
[patent_app_country] => US
[patent_app_date] => 2021-02-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 17
[patent_no_of_words] => 4401
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 106
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17179767
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/179767 | Determining mechanical reliability of electronic packages assembled with thermal pads | Feb 18, 2021 | Issued |
Array
(
[id] => 18087638
[patent_doc_number] => 11537775
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2022-12-27
[patent_title] => Timing and placement co-optimization for engineering change order (ECO) cells
[patent_app_type] => utility
[patent_app_number] => 17/176987
[patent_app_country] => US
[patent_app_date] => 2021-02-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 20
[patent_no_of_words] => 6469
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 174
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17176987
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/176987 | Timing and placement co-optimization for engineering change order (ECO) cells | Feb 15, 2021 | Issued |
Array
(
[id] => 17346072
[patent_doc_number] => 20220012403
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-01-13
[patent_title] => SEMICONDUCTOR CHIP DESIGN METHOD AND COMPUTING DEVICE FOR PERFORMING THE SAME
[patent_app_type] => utility
[patent_app_number] => 17/171267
[patent_app_country] => US
[patent_app_date] => 2021-02-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8411
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17171267
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/171267 | Semiconductor chip design method and computing device for performing the same | Feb 8, 2021 | Issued |
Array
(
[id] => 17907668
[patent_doc_number] => 11461523
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2022-10-04
[patent_title] => Glitch analysis and glitch power estimation system
[patent_app_type] => utility
[patent_app_number] => 17/169375
[patent_app_country] => US
[patent_app_date] => 2021-02-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 14
[patent_no_of_words] => 13045
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 95
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17169375
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/169375 | Glitch analysis and glitch power estimation system | Feb 4, 2021 | Issued |
Array
(
[id] => 17606211
[patent_doc_number] => 11334701
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-05-17
[patent_title] => Method for comprehensive integration verification of mixed-signal circuits
[patent_app_type] => utility
[patent_app_number] => 17/168230
[patent_app_country] => US
[patent_app_date] => 2021-02-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 10
[patent_no_of_words] => 5143
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 204
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17168230
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/168230 | Method for comprehensive integration verification of mixed-signal circuits | Feb 4, 2021 | Issued |
Array
(
[id] => 18086914
[patent_doc_number] => 11537043
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-12-27
[patent_title] => Reduction or elimination of pattern placement error in metrology measurements
[patent_app_type] => utility
[patent_app_number] => 17/161645
[patent_app_country] => US
[patent_app_date] => 2021-01-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 6232
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 74
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17161645
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/161645 | Reduction or elimination of pattern placement error in metrology measurements | Jan 27, 2021 | Issued |
Array
(
[id] => 16994322
[patent_doc_number] => 20210232742
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-07-29
[patent_title] => DETECTING TIMING VIOLATIONS IN EMULATION USING FIELD PROGRAMMABLE GATE ARRAY (FPGA) REPROGRAMMING
[patent_app_type] => utility
[patent_app_number] => 17/159056
[patent_app_country] => US
[patent_app_date] => 2021-01-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10640
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 121
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17159056
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/159056 | Detecting timing violations in emulation using field programmable gate array (FPGA) reprogramming | Jan 25, 2021 | Issued |
Array
(
[id] => 17528921
[patent_doc_number] => 11301610
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-04-12
[patent_title] => Methods for modeling of a design in reticle enhancement technology
[patent_app_type] => utility
[patent_app_number] => 17/248325
[patent_app_country] => US
[patent_app_date] => 2021-01-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 20
[patent_figures_cnt] => 25
[patent_no_of_words] => 21530
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 198
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17248325
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/248325 | Methods for modeling of a design in reticle enhancement technology | Jan 19, 2021 | Issued |
Array
(
[id] => 17682694
[patent_doc_number] => 11366950
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2022-06-21
[patent_title] => Tiled datamesh architecture
[patent_app_type] => utility
[patent_app_number] => 17/148941
[patent_app_country] => US
[patent_app_date] => 2021-01-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 7
[patent_no_of_words] => 6736
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 128
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17148941
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/148941 | Tiled datamesh architecture | Jan 13, 2021 | Issued |
Array
(
[id] => 16812943
[patent_doc_number] => 20210135498
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-05-06
[patent_title] => Wireless Charging Control Method, and Wireless Charging Transmitter and System
[patent_app_type] => utility
[patent_app_number] => 17/144764
[patent_app_country] => US
[patent_app_date] => 2021-01-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 11433
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -16
[patent_words_short_claim] => 93
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17144764
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/144764 | Wireless Charging Control Method, and Wireless Charging Transmitter and System | Jan 7, 2021 | Pending |
Array
(
[id] => 17238644
[patent_doc_number] => 11182524
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2021-11-23
[patent_title] => Fixing device for clock tree and fixing method thereof
[patent_app_type] => utility
[patent_app_number] => 17/144165
[patent_app_country] => US
[patent_app_date] => 2021-01-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 12
[patent_no_of_words] => 3983
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 124
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17144165
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/144165 | Fixing device for clock tree and fixing method thereof | Jan 7, 2021 | Issued |
Array
(
[id] => 17651753
[patent_doc_number] => 11354483
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2022-06-07
[patent_title] => Parasitic representation of large scale IC packages and boards
[patent_app_type] => utility
[patent_app_number] => 17/142381
[patent_app_country] => US
[patent_app_date] => 2021-01-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 7
[patent_no_of_words] => 6835
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 199
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17142381
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/142381 | Parasitic representation of large scale IC packages and boards | Jan 5, 2021 | Issued |