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Ronnie Kirby Jordan

Examiner (ID: 4379)

Most Active Art Unit
1747
Art Unit(s)
1747, 4146
Total Applications
116
Issued Applications
43
Pending Applications
52
Abandoned Applications
21

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17528923 [patent_doc_number] => 11301612 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-04-12 [patent_title] => Method and apparatus for predicting electrical values in electronic circuits [patent_app_type] => utility [patent_app_number] => 17/140086 [patent_app_country] => US [patent_app_date] => 2021-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 16 [patent_no_of_words] => 7332 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 219 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17140086 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/140086
Method and apparatus for predicting electrical values in electronic circuits Jan 2, 2021 Issued
Array ( [id] => 17395085 [patent_doc_number] => 11244099 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-02-08 [patent_title] => Machine-learning based prediction method for iterative clustering during clock tree synthesis [patent_app_type] => utility [patent_app_number] => 17/139675 [patent_app_country] => US [patent_app_date] => 2020-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7105 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17139675 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/139675
Machine-learning based prediction method for iterative clustering during clock tree synthesis Dec 30, 2020 Issued
Array ( [id] => 17253209 [patent_doc_number] => 11188702 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-11-30 [patent_title] => Dynamic weighting scheme for local cluster refinement [patent_app_type] => utility [patent_app_number] => 17/139617 [patent_app_country] => US [patent_app_date] => 2020-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7208 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 204 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17139617 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/139617
Dynamic weighting scheme for local cluster refinement Dec 30, 2020 Issued
Array ( [id] => 17573241 [patent_doc_number] => 11321514 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-05-03 [patent_title] => Macro clock latency computation in multiple iteration clock tree synthesis [patent_app_type] => utility [patent_app_number] => 17/139612 [patent_app_country] => US [patent_app_date] => 2020-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6369 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17139612 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/139612
Macro clock latency computation in multiple iteration clock tree synthesis Dec 30, 2020 Issued
Array ( [id] => 18816871 [patent_doc_number] => 20230391211 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-07 [patent_title] => CHARGING OF AN AGV [patent_app_type] => utility [patent_app_number] => 18/259027 [patent_app_country] => US [patent_app_date] => 2020-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2021 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18259027 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/259027
CHARGING OF AN AGV Dec 28, 2020 Pending
Array ( [id] => 16765976 [patent_doc_number] => 20210111558 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-15 [patent_title] => ENERGY STORAGE SYSTEM AND SELF-START METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/129609 [patent_app_country] => US [patent_app_date] => 2020-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5942 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17129609 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/129609
Energy storage system and self-start method thereof Dec 20, 2020 Issued
Array ( [id] => 17499719 [patent_doc_number] => 11288425 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-03-29 [patent_title] => Path-based timing driven placement using iterative pseudo netlist changes [patent_app_type] => utility [patent_app_number] => 17/124429 [patent_app_country] => US [patent_app_date] => 2020-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 10876 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17124429 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/124429
Path-based timing driven placement using iterative pseudo netlist changes Dec 15, 2020 Issued
Array ( [id] => 17675332 [patent_doc_number] => 20220188499 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-16 [patent_title] => INTEGRATED INPUT/OUTPUT PAD AND ANALOG MULTIPLEXER ARCHITECTURE [patent_app_type] => utility [patent_app_number] => 17/124283 [patent_app_country] => US [patent_app_date] => 2020-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3251 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 43 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17124283 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/124283
Integrated input/output pad and analog multiplexer architecture Dec 15, 2020 Issued
Array ( [id] => 16730080 [patent_doc_number] => 20210097227 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-01 [patent_title] => ELECTROMIGRATION EVALUATION METHODOLOGY WITH CONSIDERATION OF BOTH SELF-HEATING AND HEAT SINK THERMAL EFFECTS [patent_app_type] => utility [patent_app_number] => 17/121312 [patent_app_country] => US [patent_app_date] => 2020-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9821 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17121312 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/121312
Electromigration evaluation methodology with consideration of both self-heating and heat sink thermal effects Dec 13, 2020 Issued
Array ( [id] => 17515900 [patent_doc_number] => 11295055 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-04-05 [patent_title] => Transmission gate structure and method [patent_app_type] => utility [patent_app_number] => 17/116745 [patent_app_country] => US [patent_app_date] => 2020-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 24274 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17116745 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/116745
Transmission gate structure and method Dec 8, 2020 Issued
Array ( [id] => 16722549 [patent_doc_number] => 20210089696 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-25 [patent_title] => SYSTEM AND METHOD FOR ESL MODELING OF MACHINE LEARNING [patent_app_type] => utility [patent_app_number] => 17/115407 [patent_app_country] => US [patent_app_date] => 2020-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8700 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17115407 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/115407
System and method for ESL modeling of machine learning Dec 7, 2020 Issued
Array ( [id] => 17366015 [patent_doc_number] => 11233046 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-01-25 [patent_title] => Logical detection of electronic circuit power sequence risks [patent_app_type] => utility [patent_app_number] => 17/106384 [patent_app_country] => US [patent_app_date] => 2020-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 12078 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 257 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17106384 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/106384
Logical detection of electronic circuit power sequence risks Nov 29, 2020 Issued
Array ( [id] => 17187557 [patent_doc_number] => 20210334442 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-10-28 [patent_title] => Method and system for visualization of 3D electronic device [patent_app_type] => utility [patent_app_number] => 17/105538 [patent_app_country] => US [patent_app_date] => 2020-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6687 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17105538 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/105538
Method and system for visualization of 3D electronic device Nov 25, 2020 Issued
Array ( [id] => 16714111 [patent_doc_number] => 20210081258 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-18 [patent_title] => Synthesis Path For Transforming Concurrent Programs Into Hardware Deployable on FPGA-Based Cloud Infrastructures [patent_app_type] => utility [patent_app_number] => 17/103862 [patent_app_country] => US [patent_app_date] => 2020-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10614 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17103862 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/103862
Synthesis Path For Transforming Concurrent Programs Into Hardware Deployable on FPGA-Based Cloud Infrastructures Nov 23, 2020 Abandoned
Array ( [id] => 16711269 [patent_doc_number] => 20210078416 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-18 [patent_title] => ELECTRIC VEHICLES AND CHARGING STATIONS [patent_app_type] => utility [patent_app_number] => 17/103639 [patent_app_country] => US [patent_app_date] => 2020-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15464 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17103639 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/103639
Electric vehicles and charging stations Nov 23, 2020 Issued
Array ( [id] => 18401250 [patent_doc_number] => 11663388 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-05-30 [patent_title] => DVD simulation using microcircuits [patent_app_type] => utility [patent_app_number] => 16/951565 [patent_app_country] => US [patent_app_date] => 2020-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 17 [patent_no_of_words] => 10696 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16951565 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/951565
DVD simulation using microcircuits Nov 17, 2020 Issued
Array ( [id] => 17744678 [patent_doc_number] => 11392749 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-07-19 [patent_title] => Integrated circuit layout generation method and system [patent_app_type] => utility [patent_app_number] => 16/950999 [patent_app_country] => US [patent_app_date] => 2020-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 19 [patent_no_of_words] => 13519 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16950999 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/950999
Integrated circuit layout generation method and system Nov 17, 2020 Issued
Array ( [id] => 17667440 [patent_doc_number] => 11361140 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-06-14 [patent_title] => Routing for length-matched nets in interposer designs [patent_app_type] => utility [patent_app_number] => 17/094790 [patent_app_country] => US [patent_app_date] => 2020-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 8652 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17094790 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/094790
Routing for length-matched nets in interposer designs Nov 9, 2020 Issued
Array ( [id] => 17573240 [patent_doc_number] => 11321513 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-05-03 [patent_title] => DVD analysis that accounts for delays [patent_app_type] => utility [patent_app_number] => 17/094602 [patent_app_country] => US [patent_app_date] => 2020-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 13 [patent_no_of_words] => 10270 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17094602 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/094602
DVD analysis that accounts for delays Nov 9, 2020 Issued
Array ( [id] => 16659613 [patent_doc_number] => 20210056250 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-02-25 [patent_title] => METHOD OF REGULATING INTEGRATED CIRCUIT TIMING AND POWER CONSUMPTION [patent_app_type] => utility [patent_app_number] => 17/093131 [patent_app_country] => US [patent_app_date] => 2020-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11848 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17093131 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/093131
Method of regulating integrated circuit timing and power consumption Nov 8, 2020 Issued
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