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Rosalynd Ann Keys

Examiner (ID: 2417, Phone: (571)272-0639 , Office: P/1671 )

Most Active Art Unit
1621
Art Unit(s)
1204, CQIC, 2899, 1621, 1699, 1671, 1622
Total Applications
1942
Issued Applications
1237
Pending Applications
80
Abandoned Applications
627

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 13862129 [patent_doc_number] => 10192789 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-01-29 [patent_title] => Methods of fabricating dual threshold voltage devices [patent_app_type] => utility [patent_app_number] => 15/865140 [patent_app_country] => US [patent_app_date] => 2018-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 33 [patent_figures_cnt] => 63 [patent_no_of_words] => 14346 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15865140 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/865140
Methods of fabricating dual threshold voltage devices Jan 7, 2018 Issued
Array ( [id] => 13862127 [patent_doc_number] => 10192788 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-01-29 [patent_title] => Methods of fabricating dual threshold voltage devices with stacked gates [patent_app_type] => utility [patent_app_number] => 15/865132 [patent_app_country] => US [patent_app_date] => 2018-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 33 [patent_figures_cnt] => 63 [patent_no_of_words] => 14342 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15865132 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/865132
Methods of fabricating dual threshold voltage devices with stacked gates Jan 7, 2018 Issued
Array ( [id] => 16194243 [patent_doc_number] => 20200235092 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-23 [patent_title] => STACKED TRANSISTOR ARCHITECTURE HAVING DIVERSE FIN GEOMETRY [patent_app_type] => utility [patent_app_number] => 16/647688 [patent_app_country] => US [patent_app_date] => 2018-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10218 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16647688 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/647688
Stacked transistor architecture having diverse fin geometry Jan 7, 2018 Issued
Array ( [id] => 13862125 [patent_doc_number] => 10192787 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-01-29 [patent_title] => Methods of fabricating contacts for cylindrical devices [patent_app_type] => utility [patent_app_number] => 15/865123 [patent_app_country] => US [patent_app_date] => 2018-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 33 [patent_figures_cnt] => 63 [patent_no_of_words] => 14369 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15865123 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/865123
Methods of fabricating contacts for cylindrical devices Jan 7, 2018 Issued
Array ( [id] => 14558525 [patent_doc_number] => 10347735 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-07-09 [patent_title] => Semiconductor device with lifetime killers and method of manufacturing the same [patent_app_type] => utility [patent_app_number] => 15/863704 [patent_app_country] => US [patent_app_date] => 2018-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 6877 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 257 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15863704 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/863704
Semiconductor device with lifetime killers and method of manufacturing the same Jan 4, 2018 Issued
Array ( [id] => 12918433 [patent_doc_number] => 20180197987 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-07-12 [patent_title] => SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 15/863480 [patent_app_country] => US [patent_app_date] => 2018-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14053 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15863480 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/863480
Semiconductor structure and fabrication method thereof Jan 4, 2018 Issued
Array ( [id] => 14542535 [patent_doc_number] => 20190206889 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-07-04 [patent_title] => MULTI-GATE STRING DRIVERS HAVING SHARED PILLAR STRUCTURE [patent_app_type] => utility [patent_app_number] => 15/858509 [patent_app_country] => US [patent_app_date] => 2017-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13870 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15858509 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/858509
Multi-gate string drivers having shared pillar structure Dec 28, 2017 Issued
Array ( [id] => 17758180 [patent_doc_number] => 11398479 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-07-26 [patent_title] => Heterogeneous Ge/III-V CMOS transistor structures [patent_app_type] => utility [patent_app_number] => 16/649799 [patent_app_country] => US [patent_app_date] => 2017-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 25 [patent_no_of_words] => 16228 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 288 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16649799 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/649799
Heterogeneous Ge/III-V CMOS transistor structures Dec 28, 2017 Issued
Array ( [id] => 16272510 [patent_doc_number] => 20200273998 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-08-27 [patent_title] => SOURCE ELECTRODE AND DRAIN ELECTRODE PROTECTION FOR NANOWIRE TRANSISTORS [patent_app_type] => utility [patent_app_number] => 16/646124 [patent_app_country] => US [patent_app_date] => 2017-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8305 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16646124 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/646124
Source electrode and drain electrode protection for nanowire transistors Dec 27, 2017 Issued
Array ( [id] => 17254230 [patent_doc_number] => 11189730 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-11-30 [patent_title] => Non-selective epitaxial source/drain deposition to reduce dopant diffusion for germanium nMOS transistors [patent_app_type] => utility [patent_app_number] => 16/649716 [patent_app_country] => US [patent_app_date] => 2017-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 28 [patent_no_of_words] => 12953 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16649716 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/649716
Non-selective epitaxial source/drain deposition to reduce dopant diffusion for germanium nMOS transistors Dec 25, 2017 Issued
Array ( [id] => 12849784 [patent_doc_number] => 20180175101 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-06-21 [patent_title] => SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING SEMICONDUCTOR STRUCTURE [patent_app_type] => utility [patent_app_number] => 15/848600 [patent_app_country] => US [patent_app_date] => 2017-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4185 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15848600 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/848600
Semiconductor structure and method for manufacturing semiconductor structure Dec 19, 2017 Issued
Array ( [id] => 14769531 [patent_doc_number] => 10396170 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-08-27 [patent_title] => Semiconductor devices and methods for forming semiconductor devices [patent_app_type] => utility [patent_app_number] => 15/848614 [patent_app_country] => US [patent_app_date] => 2017-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 7184 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15848614 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/848614
Semiconductor devices and methods for forming semiconductor devices Dec 19, 2017 Issued
Array ( [id] => 15857247 [patent_doc_number] => 10643920 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-05-05 [patent_title] => Lid for semiconductor electronic package [patent_app_type] => utility [patent_app_number] => 15/848627 [patent_app_country] => US [patent_app_date] => 2017-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5073 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15848627 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/848627
Lid for semiconductor electronic package Dec 19, 2017 Issued
Array ( [id] => 14707501 [patent_doc_number] => 10381513 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-08-13 [patent_title] => Enhanced light extraction [patent_app_type] => utility [patent_app_number] => 15/847760 [patent_app_country] => US [patent_app_date] => 2017-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 19 [patent_no_of_words] => 4640 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15847760 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/847760
Enhanced light extraction Dec 18, 2017 Issued
Array ( [id] => 14828171 [patent_doc_number] => 10411102 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-09-10 [patent_title] => Semiconductor device and manufacturing method thereof [patent_app_type] => utility [patent_app_number] => 15/841891 [patent_app_country] => US [patent_app_date] => 2017-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 37 [patent_figures_cnt] => 60 [patent_no_of_words] => 26638 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15841891 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/841891
Semiconductor device and manufacturing method thereof Dec 13, 2017 Issued
Array ( [id] => 16148167 [patent_doc_number] => 10707160 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-07-07 [patent_title] => Electrical connectivity of die to a host substrate [patent_app_type] => utility [patent_app_number] => 15/817712 [patent_app_country] => US [patent_app_date] => 2017-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 12869 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 376 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15817712 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/817712
Electrical connectivity of die to a host substrate Nov 19, 2017 Issued
Array ( [id] => 12236243 [patent_doc_number] => 20180069106 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-03-08 [patent_title] => 'FABRICATION OF INTEGRATED CIRCUIT STRUCTURES FOR BIPOLOR TRANSISTORS' [patent_app_type] => utility [patent_app_number] => 15/806532 [patent_app_country] => US [patent_app_date] => 2017-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 9143 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15806532 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/806532
Fabrication of integrated circuit structures for bipolar transistors Nov 7, 2017 Issued
Array ( [id] => 12243523 [patent_doc_number] => 20180076385 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-03-15 [patent_title] => 'METHOD OF MANUFACTURING PRESSURE SENSOR, DEPOSITION SYSTEM, AND ANNEALING SYSTEM' [patent_app_type] => utility [patent_app_number] => 15/805389 [patent_app_country] => US [patent_app_date] => 2017-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 51 [patent_figures_cnt] => 51 [patent_no_of_words] => 35453 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15805389 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/805389
METHOD OF MANUFACTURING PRESSURE SENSOR, DEPOSITION SYSTEM, AND ANNEALING SYSTEM Nov 6, 2017 Abandoned
Array ( [id] => 16173012 [patent_doc_number] => 10714592 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-07-14 [patent_title] => Method of manufacturing a semiconductor device and a semiconductor device [patent_app_type] => utility [patent_app_number] => 15/798270 [patent_app_country] => US [patent_app_date] => 2017-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 33 [patent_figures_cnt] => 73 [patent_no_of_words] => 13047 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 237 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15798270 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/798270
Method of manufacturing a semiconductor device and a semiconductor device Oct 29, 2017 Issued
Array ( [id] => 12188760 [patent_doc_number] => 20180047695 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-02-15 [patent_title] => 'SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 15/797124 [patent_app_country] => US [patent_app_date] => 2017-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 31 [patent_no_of_words] => 24030 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15797124 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/797124
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF Oct 29, 2017 Abandoned
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