Search

Rosalynd Ann Keys

Examiner (ID: 2417, Phone: (571)272-0639 , Office: P/1671 )

Most Active Art Unit
1621
Art Unit(s)
1204, CQIC, 2899, 1621, 1699, 1671, 1622
Total Applications
1942
Issued Applications
1237
Pending Applications
80
Abandoned Applications
627

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 14238035 [patent_doc_number] => 20190131190 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-02 [patent_title] => METHOD FOR FORMING SEMICONDUCTOR DEVICE STRUCTURE WITH OVERLAY GRATING [patent_app_type] => utility [patent_app_number] => 15/797953 [patent_app_country] => US [patent_app_date] => 2017-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8174 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 243 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15797953 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/797953
Method for forming semiconductor device structure with overlay grating Oct 29, 2017 Issued
Array ( [id] => 14237917 [patent_doc_number] => 20190131131 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-02 [patent_title] => METHOD OF FORMING FUNNEL-LIKE OPENING FOR SEMICONDUCTOR DEVICE STRUCTURE [patent_app_type] => utility [patent_app_number] => 15/797873 [patent_app_country] => US [patent_app_date] => 2017-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5653 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15797873 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/797873
Method of forming funnel-like opening for semiconductor device structure Oct 29, 2017 Issued
Array ( [id] => 13755239 [patent_doc_number] => 10170574 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-01-01 [patent_title] => Hybrid source and drain contact formation using metal liner and metal insulator semiconductor contacts [patent_app_type] => utility [patent_app_number] => 15/792206 [patent_app_country] => US [patent_app_date] => 2017-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 15 [patent_no_of_words] => 9167 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15792206 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/792206
Hybrid source and drain contact formation using metal liner and metal insulator semiconductor contacts Oct 23, 2017 Issued
Array ( [id] => 13214655 [patent_doc_number] => 10121703 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-11-06 [patent_title] => Contact structure and extension formation for III-V nFET [patent_app_type] => utility [patent_app_number] => 15/789972 [patent_app_country] => US [patent_app_date] => 2017-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 16 [patent_no_of_words] => 4073 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 286 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15789972 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/789972
Contact structure and extension formation for III-V nFET Oct 20, 2017 Issued
Array ( [id] => 12650256 [patent_doc_number] => 20180108583 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-04-19 [patent_title] => DEVICE CHIP, ACCOMMODATING TRAY, AND METHOD OF ACCOMMODATING DEVICE CHIPS [patent_app_type] => utility [patent_app_number] => 15/730971 [patent_app_country] => US [patent_app_date] => 2017-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3499 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 18 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15730971 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/730971
DEVICE CHIP, ACCOMMODATING TRAY, AND METHOD OF ACCOMMODATING DEVICE CHIPS Oct 11, 2017 Abandoned
Array ( [id] => 15950925 [patent_doc_number] => 10663361 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-05-26 [patent_title] => Systems and methods for tactile sensing [patent_app_type] => utility [patent_app_number] => 15/782303 [patent_app_country] => US [patent_app_date] => 2017-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 27 [patent_no_of_words] => 7313 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15782303 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/782303
Systems and methods for tactile sensing Oct 11, 2017 Issued
Array ( [id] => 12554175 [patent_doc_number] => 10014283 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-07-03 [patent_title] => High heat dissipation stacked chip package structure and the manufacture method thereof [patent_app_type] => utility [patent_app_number] => 15/782239 [patent_app_country] => US [patent_app_date] => 2017-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4054 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 354 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15782239 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/782239
High heat dissipation stacked chip package structure and the manufacture method thereof Oct 11, 2017 Issued
Array ( [id] => 12669025 [patent_doc_number] => 20180114841 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-04-26 [patent_title] => POWER SEMICONDUCTOR DEVICE TERMINATION STRUCTURE [patent_app_type] => utility [patent_app_number] => 15/782041 [patent_app_country] => US [patent_app_date] => 2017-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6852 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 287 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15782041 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/782041
Power semiconductor device termination structure Oct 11, 2017 Issued
Array ( [id] => 16575049 [patent_doc_number] => 10896977 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-01-19 [patent_title] => Composite oxide semiconductor and transistor [patent_app_type] => utility [patent_app_number] => 15/782146 [patent_app_country] => US [patent_app_date] => 2017-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 52 [patent_figures_cnt] => 165 [patent_no_of_words] => 42793 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15782146 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/782146
Composite oxide semiconductor and transistor Oct 11, 2017 Issued
Array ( [id] => 14854845 [patent_doc_number] => 10416142 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-09-17 [patent_title] => Optoelectronic device for the selective detection of volatile organic compounds and related manufacturing process [patent_app_type] => utility [patent_app_number] => 15/782626 [patent_app_country] => US [patent_app_date] => 2017-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 28 [patent_no_of_words] => 7011 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15782626 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/782626
Optoelectronic device for the selective detection of volatile organic compounds and related manufacturing process Oct 11, 2017 Issued
Array ( [id] => 13293287 [patent_doc_number] => 10157844 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-12-18 [patent_title] => FinFET device having oxide layer among interlayer dielectric layer [patent_app_type] => utility [patent_app_number] => 15/730803 [patent_app_country] => US [patent_app_date] => 2017-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4771 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15730803 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/730803
FinFET device having oxide layer among interlayer dielectric layer Oct 11, 2017 Issued
Array ( [id] => 14672351 [patent_doc_number] => 10374098 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-08-06 [patent_title] => Semiconductor device [patent_app_type] => utility [patent_app_number] => 15/782165 [patent_app_country] => US [patent_app_date] => 2017-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 33 [patent_figures_cnt] => 78 [patent_no_of_words] => 35607 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15782165 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/782165
Semiconductor device Oct 11, 2017 Issued
Array ( [id] => 12779173 [patent_doc_number] => 20180151559 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-31 [patent_title] => INTEGRATED CIRCUIT, SYSTEM FOR AND METHOD OF FORMING AN INTEGRATED CIRCUIT [patent_app_type] => utility [patent_app_number] => 15/782183 [patent_app_country] => US [patent_app_date] => 2017-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15299 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15782183 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/782183
Integrated circuit, system for and method of forming an integrated circuit Oct 11, 2017 Issued
Array ( [id] => 17196207 [patent_doc_number] => 11164974 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-11-02 [patent_title] => Channel layer formed in an art trench [patent_app_type] => utility [patent_app_number] => 16/631363 [patent_app_country] => US [patent_app_date] => 2017-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 24 [patent_no_of_words] => 18138 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16631363 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/631363
Channel layer formed in an art trench Sep 28, 2017 Issued
Array ( [id] => 16973813 [patent_doc_number] => 11069795 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-07-20 [patent_title] => Transistors with channel and sub-channel regions with distinct compositions and dimensions [patent_app_type] => utility [patent_app_number] => 16/636206 [patent_app_country] => US [patent_app_date] => 2017-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 19 [patent_no_of_words] => 13443 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16636206 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/636206
Transistors with channel and sub-channel regions with distinct compositions and dimensions Sep 27, 2017 Issued
Array ( [id] => 16846117 [patent_doc_number] => 11018214 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-05-25 [patent_title] => Display device [patent_app_type] => utility [patent_app_number] => 16/651928 [patent_app_country] => US [patent_app_date] => 2017-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5897 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 388 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16651928 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/651928
Display device Sep 27, 2017 Issued
Array ( [id] => 17818711 [patent_doc_number] => 11424335 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-08-23 [patent_title] => Group III-V semiconductor devices having dual workfunction gate electrodes [patent_app_type] => utility [patent_app_number] => 16/629555 [patent_app_country] => US [patent_app_date] => 2017-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 17 [patent_no_of_words] => 6793 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16629555 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/629555
Group III-V semiconductor devices having dual workfunction gate electrodes Sep 25, 2017 Issued
Array ( [id] => 13862405 [patent_doc_number] => 10192928 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-01-29 [patent_title] => Semiconductor device and method of manufacturing the same [patent_app_type] => utility [patent_app_number] => 15/706598 [patent_app_country] => US [patent_app_date] => 2017-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 18 [patent_no_of_words] => 4710 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 316 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15706598 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/706598
Semiconductor device and method of manufacturing the same Sep 14, 2017 Issued
Array ( [id] => 12615141 [patent_doc_number] => 20180096877 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-04-05 [patent_title] => MULTI-CHIP PACKAGE ASSEMBLY [patent_app_type] => utility [patent_app_number] => 15/695398 [patent_app_country] => US [patent_app_date] => 2017-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5450 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15695398 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/695398
Multi-chip package assembly Sep 4, 2017 Issued
Array ( [id] => 14333097 [patent_doc_number] => 10297577 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-05-21 [patent_title] => Semiconductor device assembly with heat transfer structure formed from semiconductor material [patent_app_type] => utility [patent_app_number] => 15/693750 [patent_app_country] => US [patent_app_date] => 2017-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4358 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15693750 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/693750
Semiconductor device assembly with heat transfer structure formed from semiconductor material Aug 31, 2017 Issued
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