Search

Roy Karl Potter

Examiner (ID: 13991, Phone: (571)272-1842 , Office: P/2822 )

Most Active Art Unit
2822
Art Unit(s)
2822, 2508, 2811, 3621
Total Applications
2584
Issued Applications
2409
Pending Applications
46
Abandoned Applications
141

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4049421 [patent_doc_number] => 05912505 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-06-15 [patent_title] => 'Semiconductor package and semiconductor device' [patent_app_type] => 1 [patent_app_number] => 8/743160 [patent_app_country] => US [patent_app_date] => 1996-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2200 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/912/05912505.pdf [firstpage_image] =>[orig_patent_app_number] => 743160 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/743160
Semiconductor package and semiconductor device Nov 3, 1996 Issued
Array ( [id] => 4184581 [patent_doc_number] => 06037669 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-14 [patent_title] => 'Staggered pad array' [patent_app_type] => 1 [patent_app_number] => 8/740758 [patent_app_country] => US [patent_app_date] => 1996-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 15 [patent_no_of_words] => 5573 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/037/06037669.pdf [firstpage_image] =>[orig_patent_app_number] => 740758 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/740758
Staggered pad array Oct 31, 1996 Issued
Array ( [id] => 3943542 [patent_doc_number] => 05872393 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-02-16 [patent_title] => 'RF semiconductor device and a method for manufacturing the same' [patent_app_type] => 1 [patent_app_number] => 8/738744 [patent_app_country] => US [patent_app_date] => 1996-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 68 [patent_no_of_words] => 19936 [patent_no_of_claims] => 41 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/872/05872393.pdf [firstpage_image] =>[orig_patent_app_number] => 738744 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/738744
RF semiconductor device and a method for manufacturing the same Oct 27, 1996 Issued
Array ( [id] => 4123667 [patent_doc_number] => 06072228 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-06 [patent_title] => 'Multi-part lead frame with dissimilar materials and method of manufacturing' [patent_app_type] => 1 [patent_app_number] => 8/738308 [patent_app_country] => US [patent_app_date] => 1996-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 20 [patent_no_of_words] => 6236 [patent_no_of_claims] => 73 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/072/06072228.pdf [firstpage_image] =>[orig_patent_app_number] => 738308 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/738308
Multi-part lead frame with dissimilar materials and method of manufacturing Oct 24, 1996 Issued
Array ( [id] => 4095174 [patent_doc_number] => 06133638 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-17 [patent_title] => 'Die-to-insert permanent connection and method of forming' [patent_app_type] => 1 [patent_app_number] => 8/736586 [patent_app_country] => US [patent_app_date] => 1996-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 3978 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/133/06133638.pdf [firstpage_image] =>[orig_patent_app_number] => 736586 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/736586
Die-to-insert permanent connection and method of forming Oct 23, 1996 Issued
Array ( [id] => 3845470 [patent_doc_number] => 05847457 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-12-08 [patent_title] => 'Structure and method of forming vias' [patent_app_type] => 1 [patent_app_number] => 8/738040 [patent_app_country] => US [patent_app_date] => 1996-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 8 [patent_no_of_words] => 1938 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/847/05847457.pdf [firstpage_image] =>[orig_patent_app_number] => 738040 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/738040
Structure and method of forming vias Oct 23, 1996 Issued
Array ( [id] => 3748518 [patent_doc_number] => 05801450 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-01 [patent_title] => 'Variable pitch stagger die for optimal density' [patent_app_type] => 1 [patent_app_number] => 8/733518 [patent_app_country] => US [patent_app_date] => 1996-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 1098 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/801/05801450.pdf [firstpage_image] =>[orig_patent_app_number] => 733518 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/733518
Variable pitch stagger die for optimal density Oct 17, 1996 Issued
08/730432 MULTI-LAYER METAL SANDWICH WITH TAPER AND REDUCED ETCH BIAS AND METHOD FOR FORMING SAME Oct 14, 1996 Abandoned
Array ( [id] => 4543343 [patent_doc_number] => RE041975 [patent_country] => US [patent_kind] => E1 [patent_issue_date] => 2010-11-30 [patent_title] => 'Interconnector line of thin film, sputter target for forming the wiring film and electronic component using the same' [patent_app_type] => reissue [patent_app_number] => 10/732888 [patent_app_country] => US [patent_app_date] => 1996-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 11542 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/RE/041/RE041975.pdf [firstpage_image] =>[orig_patent_app_number] => 10732888 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/732888
Interconnector line of thin film, sputter target for forming the wiring film and electronic component using the same Oct 13, 1996 Issued
Array ( [id] => 3949989 [patent_doc_number] => 05990513 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-23 [patent_title] => 'Yield enhancement technique for integrated circuit processing to reduce effects of undesired dielectric moisture retention and subsequent hydrogen out-diffusion' [patent_app_type] => 1 [patent_app_number] => 8/728256 [patent_app_country] => US [patent_app_date] => 1996-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 4049 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/990/05990513.pdf [firstpage_image] =>[orig_patent_app_number] => 728256 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/728256
Yield enhancement technique for integrated circuit processing to reduce effects of undesired dielectric moisture retention and subsequent hydrogen out-diffusion Oct 7, 1996 Issued
Array ( [id] => 3820967 [patent_doc_number] => 05789811 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-08-04 [patent_title] => 'Surface mount peripheral leaded and ball grid array package' [patent_app_type] => 1 [patent_app_number] => 8/725735 [patent_app_country] => US [patent_app_date] => 1996-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 3143 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 217 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/789/05789811.pdf [firstpage_image] =>[orig_patent_app_number] => 725735 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/725735
Surface mount peripheral leaded and ball grid array package Oct 3, 1996 Issued
Array ( [id] => 3801796 [patent_doc_number] => 05828096 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-10-27 [patent_title] => 'Semiconductor device having a contact hole' [patent_app_type] => 1 [patent_app_number] => 8/726314 [patent_app_country] => US [patent_app_date] => 1996-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 17 [patent_no_of_words] => 4872 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/828/05828096.pdf [firstpage_image] =>[orig_patent_app_number] => 726314 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/726314
Semiconductor device having a contact hole Oct 1, 1996 Issued
08/720637 LAMINATED GATE MASK ROM DEVICE Oct 1, 1996 Abandoned
Array ( [id] => 3953276 [patent_doc_number] => 05998861 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-07 [patent_title] => 'Semiconductor device having ball grid array' [patent_app_type] => 1 [patent_app_number] => 8/721012 [patent_app_country] => US [patent_app_date] => 1996-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 52 [patent_no_of_words] => 15280 [patent_no_of_claims] => 49 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/998/05998861.pdf [firstpage_image] =>[orig_patent_app_number] => 721012 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/721012
Semiconductor device having ball grid array Sep 25, 1996 Issued
Array ( [id] => 4132827 [patent_doc_number] => 06127735 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-03 [patent_title] => 'Interconnect for low temperature chip attachment' [patent_app_type] => 1 [patent_app_number] => 8/710992 [patent_app_country] => US [patent_app_date] => 1996-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 3958 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/127/06127735.pdf [firstpage_image] =>[orig_patent_app_number] => 710992 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/710992
Interconnect for low temperature chip attachment Sep 24, 1996 Issued
Array ( [id] => 3845579 [patent_doc_number] => 05744852 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-04-28 [patent_title] => 'Bonded wafer' [patent_app_type] => 1 [patent_app_number] => 8/710694 [patent_app_country] => US [patent_app_date] => 1996-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 4 [patent_no_of_words] => 2278 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/744/05744852.pdf [firstpage_image] =>[orig_patent_app_number] => 710694 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/710694
Bonded wafer Sep 18, 1996 Issued
Array ( [id] => 3865155 [patent_doc_number] => 05793111 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-08-11 [patent_title] => 'Barrier and landing pad structure in an integrated circuit' [patent_app_type] => 1 [patent_app_number] => 8/709356 [patent_app_country] => US [patent_app_date] => 1996-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 3287 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/793/05793111.pdf [firstpage_image] =>[orig_patent_app_number] => 709356 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/709356
Barrier and landing pad structure in an integrated circuit Sep 5, 1996 Issued
Array ( [id] => 3943556 [patent_doc_number] => 05872394 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-02-16 [patent_title] => 'Lead frame' [patent_app_type] => 1 [patent_app_number] => 8/708706 [patent_app_country] => US [patent_app_date] => 1996-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 39 [patent_no_of_words] => 5182 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/872/05872394.pdf [firstpage_image] =>[orig_patent_app_number] => 708706 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/708706
Lead frame Sep 4, 1996 Issued
Array ( [id] => 3830240 [patent_doc_number] => 05731620 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-03-24 [patent_title] => 'Semiconductor device with reduced parasitic substrate capacitance' [patent_app_type] => 1 [patent_app_number] => 8/708654 [patent_app_country] => US [patent_app_date] => 1996-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 32 [patent_no_of_words] => 7753 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/731/05731620.pdf [firstpage_image] =>[orig_patent_app_number] => 708654 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/708654
Semiconductor device with reduced parasitic substrate capacitance Sep 4, 1996 Issued
08/711668 MULTI-LAYER LEAD FRAME FOR A SEMICONDUCTOR DEVICE Sep 3, 1996 Abandoned
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