Search

Roy Karl Potter

Examiner (ID: 13991, Phone: (571)272-1842 , Office: P/2822 )

Most Active Art Unit
2822
Art Unit(s)
2822, 2508, 2811, 3621
Total Applications
2584
Issued Applications
2409
Pending Applications
46
Abandoned Applications
141

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 9600866 [patent_doc_number] => 20140197549 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-07-17 [patent_title] => 'SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 14/154390 [patent_app_country] => US [patent_app_date] => 2014-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4564 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14154390 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/154390
SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME Jan 13, 2014 Abandoned
Array ( [id] => 9796654 [patent_doc_number] => 20150008598 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-01-08 [patent_title] => 'ALIGNMENT MARK, PHOTOMASK, AND METHOD FOR FORMING ALIGNMENT MARK' [patent_app_type] => utility [patent_app_number] => 14/152116 [patent_app_country] => US [patent_app_date] => 2014-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5239 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14152116 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/152116
Alignment mark, photomask, and method for forming alignment mark Jan 9, 2014 Issued
Array ( [id] => 10073678 [patent_doc_number] => 09112043 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-08-18 [patent_title] => 'Display device and manufacturing method thereof' [patent_app_type] => utility [patent_app_number] => 14/151183 [patent_app_country] => US [patent_app_date] => 2014-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 57 [patent_no_of_words] => 15626 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14151183 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/151183
Display device and manufacturing method thereof Jan 8, 2014 Issued
Array ( [id] => 10206197 [patent_doc_number] => 20150091185 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-04-02 [patent_title] => 'SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME' [patent_app_type] => utility [patent_app_number] => 14/148068 [patent_app_country] => US [patent_app_date] => 2014-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2926 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14148068 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/148068
Semiconductor device and method for forming the same Jan 5, 2014 Issued
Array ( [id] => 10888559 [patent_doc_number] => 08912556 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-12-16 [patent_title] => 'Light emitting device and method of manufacturing the same' [patent_app_type] => utility [patent_app_number] => 14/147947 [patent_app_country] => US [patent_app_date] => 2014-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 13 [patent_no_of_words] => 5410 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14147947 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/147947
Light emitting device and method of manufacturing the same Jan 5, 2014 Issued
Array ( [id] => 10230470 [patent_doc_number] => 20150115464 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-04-30 [patent_title] => 'Chip on Package Structure and Method' [patent_app_type] => utility [patent_app_number] => 14/147316 [patent_app_country] => US [patent_app_date] => 2014-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 9445 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14147316 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/147316
Chip on package structure and method Jan 2, 2014 Issued
Array ( [id] => 11036342 [patent_doc_number] => 20160233298 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-08-11 [patent_title] => 'Self-Aligned Gate Edge and Local Interconnect and Method to Fabricate Same' [patent_app_type] => utility [patent_app_number] => 15/024750 [patent_app_country] => US [patent_app_date] => 2013-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 8618 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15024750 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/024750
Self-aligned gate edge and local interconnect and method to fabricate same Dec 18, 2013 Issued
Array ( [id] => 10929955 [patent_doc_number] => 20140332977 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-11-13 [patent_title] => 'SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 14/135076 [patent_app_country] => US [patent_app_date] => 2013-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3189 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14135076 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/135076
Semiconductor device Dec 18, 2013 Issued
Array ( [id] => 10086519 [patent_doc_number] => 09123874 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-09-01 [patent_title] => 'Light emitting device packages with improved heat transfer' [patent_app_type] => utility [patent_app_number] => 14/094341 [patent_app_country] => US [patent_app_date] => 2013-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 26 [patent_no_of_words] => 9119 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14094341 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/094341
Light emitting device packages with improved heat transfer Dec 1, 2013 Issued
Array ( [id] => 12202683 [patent_doc_number] => 09905757 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-02-27 [patent_title] => 'Nonlinear memristor devices with three-layer selectors' [patent_app_type] => utility [patent_app_number] => 15/032913 [patent_app_country] => US [patent_app_date] => 2013-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 3873 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15032913 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/032913
Nonlinear memristor devices with three-layer selectors Nov 11, 2013 Issued
Array ( [id] => 9682713 [patent_doc_number] => 20140239476 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-08-28 [patent_title] => 'SEMICONDUCTOR DEVICE WITH INTEGRAL HEAT SINK' [patent_app_type] => utility [patent_app_number] => 14/077205 [patent_app_country] => US [patent_app_date] => 2013-11-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2962 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14077205 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/077205
Semiconductor device with integral heat sink Nov 10, 2013 Issued
Array ( [id] => 9552928 [patent_doc_number] => 08759980 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-06-24 [patent_title] => 'Forming array contacts in semiconductor memories' [patent_app_type] => utility [patent_app_number] => 14/066340 [patent_app_country] => US [patent_app_date] => 2013-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 1754 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14066340 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/066340
Forming array contacts in semiconductor memories Oct 28, 2013 Issued
Array ( [id] => 9965430 [patent_doc_number] => 09013047 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-04-21 [patent_title] => 'Semiconductor device' [patent_app_type] => utility [patent_app_number] => 14/056148 [patent_app_country] => US [patent_app_date] => 2013-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 3899 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14056148 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/056148
Semiconductor device Oct 16, 2013 Issued
Array ( [id] => 9418851 [patent_doc_number] => 20140103501 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-04-17 [patent_title] => 'CIRCUIT BOARD WITH TWINNED CU CIRCUIT LAYER AND METHOD FOR MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 14/055456 [patent_app_country] => US [patent_app_date] => 2013-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4999 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14055456 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/055456
Circuit board with twinned CU circuit layer and method for manufacturing the same Oct 15, 2013 Issued
Array ( [id] => 9291328 [patent_doc_number] => 20140034962 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-02-06 [patent_title] => 'Normally-Off Compound Semiconductor Tunnel Transistor with a Plurality of Charge Carrier Gases' [patent_app_type] => utility [patent_app_number] => 14/051935 [patent_app_country] => US [patent_app_date] => 2013-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5539 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14051935 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/051935
Normally-off compound semiconductor tunnel transistor with a plurality of charge carrier gases Oct 10, 2013 Issued
Array ( [id] => 9883217 [patent_doc_number] => 08969984 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-03-03 [patent_title] => 'Magnetic tunnel junction device' [patent_app_type] => utility [patent_app_number] => 14/048704 [patent_app_country] => US [patent_app_date] => 2013-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6099 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14048704 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/048704
Magnetic tunnel junction device Oct 7, 2013 Issued
Array ( [id] => 9335090 [patent_doc_number] => 20140061872 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-03-06 [patent_title] => 'Method for Reducing Thickness of Interfacial Layer, Method for Forming High Dielectric Constant Gate Insulating Film, High Dielectric Constant Gate Insulating Film, High Dielectric Constant Gate Oxide Film, and Transistor Having High Dielectric Constant Gate Oxide Film' [patent_app_type] => utility [patent_app_number] => 14/046339 [patent_app_country] => US [patent_app_date] => 2013-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6650 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14046339 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/046339
Method for reducing thickness of interfacial layer, method for forming high dielectric constant gate insulating film, high dielectric constant gate insulating film, high dielectric constant gate oxide film, and transistor having high dielectric constant gate oxide film Oct 3, 2013 Issued
Array ( [id] => 10876181 [patent_doc_number] => 08900966 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-12-02 [patent_title] => 'Alignment for backside illumination sensor' [patent_app_type] => utility [patent_app_number] => 14/044716 [patent_app_country] => US [patent_app_date] => 2013-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 17 [patent_no_of_words] => 8490 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14044716 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/044716
Alignment for backside illumination sensor Oct 1, 2013 Issued
Array ( [id] => 11014237 [patent_doc_number] => 20160211190 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-07-21 [patent_title] => 'DUAL-SIDED DIE PACKAGES' [patent_app_type] => utility [patent_app_number] => 14/914998 [patent_app_country] => US [patent_app_date] => 2013-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5351 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14914998 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/914998
Dual-sided die packages Sep 26, 2013 Issued
Array ( [id] => 10066762 [patent_doc_number] => 09105620 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-08-11 [patent_title] => 'Integrated circuit packaging system with routable traces and method of manufacture thereof' [patent_app_type] => utility [patent_app_number] => 14/038577 [patent_app_country] => US [patent_app_date] => 2013-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 47 [patent_no_of_words] => 18871 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14038577 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/038577
Integrated circuit packaging system with routable traces and method of manufacture thereof Sep 25, 2013 Issued
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