Search

Roy Karl Potter

Examiner (ID: 13991, Phone: (571)272-1842 , Office: P/2822 )

Most Active Art Unit
2822
Art Unit(s)
2822, 2508, 2811, 3621
Total Applications
2584
Issued Applications
2409
Pending Applications
46
Abandoned Applications
141

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 10286367 [patent_doc_number] => 20150171365 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-06-18 [patent_title] => 'ELECTRONIC ELEMENT SEALING METHOD AND BONDED SUBSTRATE' [patent_app_type] => utility [patent_app_number] => 14/407721 [patent_app_country] => US [patent_app_date] => 2013-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 11840 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14407721 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/407721
Electronic element sealing method and bonded substrate Jun 13, 2013 Issued
Array ( [id] => 9350251 [patent_doc_number] => 08669142 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-03-11 [patent_title] => 'Method of manufacturing package structure' [patent_app_type] => utility [patent_app_number] => 13/906355 [patent_app_country] => US [patent_app_date] => 2013-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 14 [patent_no_of_words] => 4863 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13906355 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/906355
Method of manufacturing package structure May 30, 2013 Issued
Array ( [id] => 9079173 [patent_doc_number] => 20130264704 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-10-10 [patent_title] => 'Semiconductor Device and Method of Confining Conductive Bump Material During Reflow with Solder Mask Patch' [patent_app_type] => utility [patent_app_number] => 13/905845 [patent_app_country] => US [patent_app_date] => 2013-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5562 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13905845 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/905845
Semiconductor device and method of confining conductive bump material during reflow with solder mask patch May 29, 2013 Issued
Array ( [id] => 9608898 [patent_doc_number] => 08786069 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-07-22 [patent_title] => 'Reconfigurable pop' [patent_app_type] => utility [patent_app_number] => 13/898952 [patent_app_country] => US [patent_app_date] => 2013-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 15 [patent_no_of_words] => 10470 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 23 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13898952 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/898952
Reconfigurable pop May 20, 2013 Issued
Array ( [id] => 9876029 [patent_doc_number] => 08963302 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-02-24 [patent_title] => 'Stacked packaged integrated circuit devices, and methods of making same' [patent_app_type] => utility [patent_app_number] => 13/898782 [patent_app_country] => US [patent_app_date] => 2013-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 1984 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 34 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13898782 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/898782
Stacked packaged integrated circuit devices, and methods of making same May 20, 2013 Issued
Array ( [id] => 10936681 [patent_doc_number] => 20140339702 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-11-20 [patent_title] => 'METAL PVD-FREE CONDUCTING STRUCTURES' [patent_app_type] => utility [patent_app_number] => 13/897956 [patent_app_country] => US [patent_app_date] => 2013-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5737 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13897956 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/897956
Metal PVD-free conducting structures May 19, 2013 Issued
Array ( [id] => 9729092 [patent_doc_number] => 20140264799 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-09-18 [patent_title] => 'POWER OVERLAY STRUCTURE AND METHOD OF MAKING SAME' [patent_app_type] => utility [patent_app_number] => 13/897638 [patent_app_country] => US [patent_app_date] => 2013-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 6231 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13897638 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/897638
Power overlay structure and method of making same May 19, 2013 Issued
Array ( [id] => 9951788 [patent_doc_number] => 09000581 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-04-07 [patent_title] => 'Semiconductor package' [patent_app_type] => utility [patent_app_number] => 13/896616 [patent_app_country] => US [patent_app_date] => 2013-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 3164 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13896616 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/896616
Semiconductor package May 16, 2013 Issued
Array ( [id] => 9648531 [patent_doc_number] => 08802541 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-08-12 [patent_title] => 'Method for low temperature wafer bonding and bonded structure' [patent_app_type] => utility [patent_app_number] => 13/896593 [patent_app_country] => US [patent_app_date] => 2013-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 24 [patent_no_of_words] => 7909 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13896593 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/896593
Method for low temperature wafer bonding and bonded structure May 16, 2013 Issued
Array ( [id] => 9613572 [patent_doc_number] => 20140203429 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-07-24 [patent_title] => 'FAN-OUT PACKAGE STRUCTURE AND METHODS FOR FORMING THE SAME' [patent_app_type] => utility [patent_app_number] => 13/896889 [patent_app_country] => US [patent_app_date] => 2013-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2960 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13896889 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/896889
Fan-out package structure and methods for forming the same May 16, 2013 Issued
Array ( [id] => 9054662 [patent_doc_number] => 20130252376 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-09-26 [patent_title] => 'FORMING DIE BACKSIDE COATING STRUCTURES WITH CORELESS PACKAGES' [patent_app_type] => utility [patent_app_number] => 13/895546 [patent_app_country] => US [patent_app_date] => 2013-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 4242 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13895546 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/895546
Forming die backside coating structures with coreless packages May 15, 2013 Issued
Array ( [id] => 9158856 [patent_doc_number] => 20130307133 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-11-21 [patent_title] => 'SEMICONDUCTOR DEVICE ASSEMBLY AND SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 13/895472 [patent_app_country] => US [patent_app_date] => 2013-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8884 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13895472 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/895472
Semiconductor device assembly and semiconductor device and method of manufacturing the same May 15, 2013 Issued
Array ( [id] => 9158885 [patent_doc_number] => 20130307162 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-11-21 [patent_title] => 'WIRING BOARD AND METHOD FOR MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 13/895834 [patent_app_country] => US [patent_app_date] => 2013-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 27 [patent_no_of_words] => 9532 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13895834 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/895834
Wiring board and method for manufacturing the same May 15, 2013 Issued
Array ( [id] => 9209637 [patent_doc_number] => 20140008814 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-01-09 [patent_title] => 'SUBSTRATE FOR SEMICONDUCTOR PACKAGE AND PROCESS FOR MANUFACTURING' [patent_app_type] => utility [patent_app_number] => 13/895704 [patent_app_country] => US [patent_app_date] => 2013-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 9300 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13895704 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/895704
Substrate for semiconductor package and process for manufacturing May 15, 2013 Issued
Array ( [id] => 9158852 [patent_doc_number] => 20130307129 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-11-21 [patent_title] => 'WIRING MEMBER AND SEMICONDUCTOR MODULE HAVING THE SAME' [patent_app_type] => utility [patent_app_number] => 13/895903 [patent_app_country] => US [patent_app_date] => 2013-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6586 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13895903 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/895903
Wiring member and semiconductor module having the same May 15, 2013 Issued
Array ( [id] => 9729241 [patent_doc_number] => 20140264948 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-09-18 [patent_title] => 'Air Trench in Packages Incorporating Hybrid Bonding' [patent_app_type] => utility [patent_app_number] => 13/895122 [patent_app_country] => US [patent_app_date] => 2013-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3232 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13895122 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/895122
Air trench in packages incorporating hybrid bonding May 14, 2013 Issued
Array ( [id] => 9639495 [patent_doc_number] => 20140217605 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-08-07 [patent_title] => 'INTERCONNECTION STRUCTURE FOR PACKAGE AND FABRICATION METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 13/894687 [patent_app_country] => US [patent_app_date] => 2013-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2953 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13894687 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/894687
Interconnection structure for package and fabrication method thereof May 14, 2013 Issued
Array ( [id] => 9051183 [patent_doc_number] => 20130248897 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-09-26 [patent_title] => 'LIGHT EMITTING DIODE WAFER-LEVEL PACKAGE WITH SELF-ALIGNING FEATURES' [patent_app_type] => utility [patent_app_number] => 13/894189 [patent_app_country] => US [patent_app_date] => 2013-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3654 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13894189 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/894189
Light emitting diode wafer-level package with self-aligning features May 13, 2013 Issued
Array ( [id] => 9649309 [patent_doc_number] => 08803329 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-08-12 [patent_title] => 'Semiconductor package and stacked semiconductor package' [patent_app_type] => utility [patent_app_number] => 13/892538 [patent_app_country] => US [patent_app_date] => 2013-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 6219 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13892538 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/892538
Semiconductor package and stacked semiconductor package May 12, 2013 Issued
Array ( [id] => 9850795 [patent_doc_number] => 08952532 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-02-10 [patent_title] => 'Integrated circuit package with spatially varied solder resist opening dimension' [patent_app_type] => utility [patent_app_number] => 13/893193 [patent_app_country] => US [patent_app_date] => 2013-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 18 [patent_no_of_words] => 6179 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13893193 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/893193
Integrated circuit package with spatially varied solder resist opening dimension May 12, 2013 Issued
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