
Roy Karl Potter
Examiner (ID: 13991, Phone: (571)272-1842 , Office: P/2822 )
| Most Active Art Unit | 2822 |
| Art Unit(s) | 2822, 2508, 2811, 3621 |
| Total Applications | 2584 |
| Issued Applications | 2409 |
| Pending Applications | 46 |
| Abandoned Applications | 141 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 10286367
[patent_doc_number] => 20150171365
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-06-18
[patent_title] => 'ELECTRONIC ELEMENT SEALING METHOD AND BONDED SUBSTRATE'
[patent_app_type] => utility
[patent_app_number] => 14/407721
[patent_app_country] => US
[patent_app_date] => 2013-06-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
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[rel_patent_id] =>[rel_patent_doc_number] =>) 14/407721 | Electronic element sealing method and bonded substrate | Jun 13, 2013 | Issued |
Array
(
[id] => 9350251
[patent_doc_number] => 08669142
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2014-03-11
[patent_title] => 'Method of manufacturing package structure'
[patent_app_type] => utility
[patent_app_number] => 13/906355
[patent_app_country] => US
[patent_app_date] => 2013-05-31
[patent_effective_date] => 0000-00-00
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/906355 | Method of manufacturing package structure | May 30, 2013 | Issued |
Array
(
[id] => 9079173
[patent_doc_number] => 20130264704
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-10-10
[patent_title] => 'Semiconductor Device and Method of Confining Conductive Bump Material During Reflow with Solder Mask Patch'
[patent_app_type] => utility
[patent_app_number] => 13/905845
[patent_app_country] => US
[patent_app_date] => 2013-05-30
[patent_effective_date] => 0000-00-00
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/905845 | Semiconductor device and method of confining conductive bump material during reflow with solder mask patch | May 29, 2013 | Issued |
Array
(
[id] => 9608898
[patent_doc_number] => 08786069
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2014-07-22
[patent_title] => 'Reconfigurable pop'
[patent_app_type] => utility
[patent_app_number] => 13/898952
[patent_app_country] => US
[patent_app_date] => 2013-05-21
[patent_effective_date] => 0000-00-00
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/898952 | Reconfigurable pop | May 20, 2013 | Issued |
Array
(
[id] => 9876029
[patent_doc_number] => 08963302
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2015-02-24
[patent_title] => 'Stacked packaged integrated circuit devices, and methods of making same'
[patent_app_type] => utility
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/898782 | Stacked packaged integrated circuit devices, and methods of making same | May 20, 2013 | Issued |
Array
(
[id] => 10936681
[patent_doc_number] => 20140339702
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[patent_kind] => A1
[patent_issue_date] => 2014-11-20
[patent_title] => 'METAL PVD-FREE CONDUCTING STRUCTURES'
[patent_app_type] => utility
[patent_app_number] => 13/897956
[patent_app_country] => US
[patent_app_date] => 2013-05-20
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/897956 | Metal PVD-free conducting structures | May 19, 2013 | Issued |
Array
(
[id] => 9729092
[patent_doc_number] => 20140264799
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-09-18
[patent_title] => 'POWER OVERLAY STRUCTURE AND METHOD OF MAKING SAME'
[patent_app_type] => utility
[patent_app_number] => 13/897638
[patent_app_country] => US
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/897638 | Power overlay structure and method of making same | May 19, 2013 | Issued |
Array
(
[id] => 9951788
[patent_doc_number] => 09000581
[patent_country] => US
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[patent_issue_date] => 2015-04-07
[patent_title] => 'Semiconductor package'
[patent_app_type] => utility
[patent_app_number] => 13/896616
[patent_app_country] => US
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/896616 | Semiconductor package | May 16, 2013 | Issued |
Array
(
[id] => 9648531
[patent_doc_number] => 08802541
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2014-08-12
[patent_title] => 'Method for low temperature wafer bonding and bonded structure'
[patent_app_type] => utility
[patent_app_number] => 13/896593
[patent_app_country] => US
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Array
(
[id] => 9613572
[patent_doc_number] => 20140203429
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-07-24
[patent_title] => 'FAN-OUT PACKAGE STRUCTURE AND METHODS FOR FORMING THE SAME'
[patent_app_type] => utility
[patent_app_number] => 13/896889
[patent_app_country] => US
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/896889 | Fan-out package structure and methods for forming the same | May 16, 2013 | Issued |
Array
(
[id] => 9054662
[patent_doc_number] => 20130252376
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-09-26
[patent_title] => 'FORMING DIE BACKSIDE COATING STRUCTURES WITH CORELESS PACKAGES'
[patent_app_type] => utility
[patent_app_number] => 13/895546
[patent_app_country] => US
[patent_app_date] => 2013-05-16
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/895546 | Forming die backside coating structures with coreless packages | May 15, 2013 | Issued |
Array
(
[id] => 9158856
[patent_doc_number] => 20130307133
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-11-21
[patent_title] => 'SEMICONDUCTOR DEVICE ASSEMBLY AND SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME'
[patent_app_type] => utility
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Array
(
[id] => 9158885
[patent_doc_number] => 20130307162
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-11-21
[patent_title] => 'WIRING BOARD AND METHOD FOR MANUFACTURING THE SAME'
[patent_app_type] => utility
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Array
(
[id] => 9209637
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[patent_title] => 'SUBSTRATE FOR SEMICONDUCTOR PACKAGE AND PROCESS FOR MANUFACTURING'
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Array
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Array
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Array
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Array
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Array
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Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/893193 | Integrated circuit package with spatially varied solder resist opening dimension | May 12, 2013 | Issued |