Search

Roy Karl Potter

Examiner (ID: 13991, Phone: (571)272-1842 , Office: P/2822 )

Most Active Art Unit
2822
Art Unit(s)
2822, 2508, 2811, 3621
Total Applications
2584
Issued Applications
2409
Pending Applications
46
Abandoned Applications
141

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 14558761 [patent_doc_number] => 10347854 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-07-09 [patent_title] => Logic circuit based on thin film transistor [patent_app_type] => utility [patent_app_number] => 15/817534 [patent_app_country] => US [patent_app_date] => 2017-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 42 [patent_no_of_words] => 9677 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15817534 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/817534
Logic circuit based on thin film transistor Nov 19, 2017 Issued
Array ( [id] => 14011839 [patent_doc_number] => 10224396 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-03-05 [patent_title] => Deep trench isolation structures [patent_app_type] => utility [patent_app_number] => 15/817629 [patent_app_country] => US [patent_app_date] => 2017-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3741 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15817629 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/817629
Deep trench isolation structures Nov 19, 2017 Issued
Array ( [id] => 15286441 [patent_doc_number] => 10515890 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-12-24 [patent_title] => Semiconductor device [patent_app_type] => utility [patent_app_number] => 15/817267 [patent_app_country] => US [patent_app_date] => 2017-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 32 [patent_no_of_words] => 10327 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 218 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15817267 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/817267
Semiconductor device Nov 18, 2017 Issued
Array ( [id] => 13976709 [patent_doc_number] => 10217721 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-02-26 [patent_title] => Dual-sided memory module with channels aligned in opposition [patent_app_type] => utility [patent_app_number] => 15/817066 [patent_app_country] => US [patent_app_date] => 2017-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 20 [patent_no_of_words] => 7120 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15817066 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/817066
Dual-sided memory module with channels aligned in opposition Nov 16, 2017 Issued
Array ( [id] => 12236288 [patent_doc_number] => 20180069151 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-03-08 [patent_title] => 'Deep Ultraviolet Light Emitting Diode' [patent_app_type] => utility [patent_app_number] => 15/797282 [patent_app_country] => US [patent_app_date] => 2017-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 7792 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15797282 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/797282
Deep ultraviolet light emitting diode Oct 29, 2017 Issued
Array ( [id] => 12693130 [patent_doc_number] => 20180122876 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-03 [patent_title] => DISPLAY DEVICE HAVING AN AUXILIARY ELECTRODE [patent_app_type] => utility [patent_app_number] => 15/791081 [patent_app_country] => US [patent_app_date] => 2017-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6840 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15791081 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/791081
Display device having an auxiliary electrode Oct 22, 2017 Issued
Array ( [id] => 12188872 [patent_doc_number] => 20180047808 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-02-15 [patent_title] => 'SELF-ALIGNED GATE EDGE AND LOCAL INTERCONNECT AND METHOD TO FABRICATE SAME' [patent_app_type] => utility [patent_app_number] => 15/789315 [patent_app_country] => US [patent_app_date] => 2017-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 8687 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15789315 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/789315
Self-aligned gate edge and local interconnect and method to fabricate same Oct 19, 2017 Issued
Array ( [id] => 14075633 [patent_doc_number] => 20190086704 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-03-21 [patent_title] => METHOD OF FORMING CRYSTALLINE ITO THIN FILM AND METHOD OF FORMING ON-CELL TYPE TOUCH PANEL [patent_app_type] => utility [patent_app_number] => 15/576024 [patent_app_country] => US [patent_app_date] => 2017-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3180 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15576024 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/576024
Method of forming crystalline ITO thin film and method of forming on-cell type touch panel Oct 11, 2017 Issued
Array ( [id] => 13784635 [patent_doc_number] => 20190005856 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-01-03 [patent_title] => MANUFACTURING METHOD OF FLEXIBLE BACKPLATE, LIQUID CRYSTAL DISPLAY PANEL, AND ORGANIC LIGHT-EMITTING DIODEDISPLAY PANEL [patent_app_type] => utility [patent_app_number] => 15/736619 [patent_app_country] => US [patent_app_date] => 2017-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3105 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 212 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15736619 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/736619
Manufacturing method of flexible backplate, liquid crystal display panel, and organic light-emitting diodedisplay panel Sep 13, 2017 Issued
Array ( [id] => 12913843 [patent_doc_number] => 20180196457 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-07-12 [patent_title] => REGENERATIVE CURRENT DETECTION CIRCUIT, CHARGE CURRENT DETECTION CIRCUIT, AND MOTOR CURRENT DETECTION SYSTEM [patent_app_type] => utility [patent_app_number] => 15/690258 [patent_app_country] => US [patent_app_date] => 2017-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6955 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15690258 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/690258
Regenerative current detection circuit, charge current detection circuit, and motor current detection system Aug 28, 2017 Issued
Array ( [id] => 12223756 [patent_doc_number] => 20180062116 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-03-01 [patent_title] => 'DISPLAY DEVICE HAVING A MICRO-CAVITY STRUCTURE AND METHOD FOR FORMING THE SAME' [patent_app_type] => utility [patent_app_number] => 15/690206 [patent_app_country] => US [patent_app_date] => 2017-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 11204 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15690206 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/690206
Display device having a micro-cavity structure and method for forming the same Aug 28, 2017 Issued
Array ( [id] => 14707091 [patent_doc_number] => 10381305 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-08-13 [patent_title] => Integrated assemblies having structures along a first pitch coupled with structures along a second pitch different from the first pitch, and methods of forming integrated assemblies [patent_app_type] => utility [patent_app_number] => 15/690209 [patent_app_country] => US [patent_app_date] => 2017-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 5366 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15690209 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/690209
Integrated assemblies having structures along a first pitch coupled with structures along a second pitch different from the first pitch, and methods of forming integrated assemblies Aug 28, 2017 Issued
Array ( [id] => 14889227 [patent_doc_number] => 10424665 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-09-24 [patent_title] => Semiconductor device and method of manufacturing the semiconductor device [patent_app_type] => utility [patent_app_number] => 15/690233 [patent_app_country] => US [patent_app_date] => 2017-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 50 [patent_no_of_words] => 22977 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 398 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15690233 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/690233
Semiconductor device and method of manufacturing the semiconductor device Aug 28, 2017 Issued
Array ( [id] => 13709103 [patent_doc_number] => 20170365506 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-12-21 [patent_title] => METHOD OF MANUFACTURING HIGH RESISTIVITY SOI WAFERS WITH CHARGE TRAPPING LAYERS BASED ON TERMINATED SI DEPOSITION [patent_app_type] => utility [patent_app_number] => 15/675001 [patent_app_country] => US [patent_app_date] => 2017-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9617 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -28 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15675001 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/675001
Method of manufacturing high resistivity SOI wafers with charge trapping layers based on terminated Si deposition Aug 10, 2017 Issued
Array ( [id] => 12376377 [patent_doc_number] => 09960354 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-05-01 [patent_title] => Method for making thin film transistor [patent_app_type] => utility [patent_app_number] => 15/662253 [patent_app_country] => US [patent_app_date] => 2017-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2809 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15662253 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/662253
Method for making thin film transistor Jul 26, 2017 Issued
Array ( [id] => 12026731 [patent_doc_number] => 20170316830 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-11-02 [patent_title] => 'LIGHT-ERASABLE EMBEDDED MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 15/638352 [patent_app_country] => US [patent_app_date] => 2017-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4371 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15638352 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/638352
Light-erasable embedded memory device and method of manufacturing the same Jun 28, 2017 Issued
Array ( [id] => 11983653 [patent_doc_number] => 20170287808 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-10-05 [patent_title] => 'DUAL-SIDED DIE PACKAGES' [patent_app_type] => utility [patent_app_number] => 15/625947 [patent_app_country] => US [patent_app_date] => 2017-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5406 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15625947 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/625947
Dual-sided die packages Jun 15, 2017 Issued
Array ( [id] => 14672303 [patent_doc_number] => 10374073 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-08-06 [patent_title] => Single electron transistor with wrap-around gate [patent_app_type] => utility [patent_app_number] => 15/623877 [patent_app_country] => US [patent_app_date] => 2017-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 16 [patent_no_of_words] => 4255 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 46 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15623877 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/623877
Single electron transistor with wrap-around gate Jun 14, 2017 Issued
Array ( [id] => 13132001 [patent_doc_number] => 10083940 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-09-25 [patent_title] => Package-on-package semiconductor device [patent_app_type] => utility [patent_app_number] => 15/622166 [patent_app_country] => US [patent_app_date] => 2017-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 32 [patent_no_of_words] => 4992 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15622166 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/622166
Package-on-package semiconductor device Jun 13, 2017 Issued
Array ( [id] => 11959369 [patent_doc_number] => 20170263521 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-09-14 [patent_title] => 'RESIN-ENCAPSULATED SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 15/605027 [patent_app_country] => US [patent_app_date] => 2017-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 7041 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15605027 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/605027
Resin-encapsulated semiconductor device May 24, 2017 Issued
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