Roy Karl Potter

Array ( [id] => 8178292 [patent_doc_number] => 08178959 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-05-15 [patent_title] => 'Process for fabricating a semiconductor component support, support and semiconductor device' [patent_app_type] => utility [patent_app_number] => 12/633724 [patent_app_country] => US [patent_app_date] => 2009-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 2714 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/178/08178959.pdf [firstpage_image] =>[orig_patent_app_number] => 12633724 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6393422 [patent_doc_number] => 20100164097 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-07-01 [patent_title] => 'Semiconductor Device and Method of Confining Conductive Bump Material During Reflow with Solder Mask Patch' [patent_app_type] => utility [patent_app_number] => 12/633531 [patent_app_country] => US [patent_app_date] => 2009-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5798 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0164/20100164097.pdf [firstpage_image] =>[orig_patent_app_number] => 12633531 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8213977 [patent_doc_number] => 08193013 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-06-05 [patent_title] => 'Semiconductor optical sensor element and method of producing the same' [patent_app_type] => utility [patent_app_number] => 12/632930 [patent_app_country] => US [patent_app_date] => 2009-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 21 [patent_no_of_words] => 7030 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/193/08193013.pdf [firstpage_image] =>[orig_patent_app_number] => 12632930 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8578294 [patent_doc_number] => 08344506 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-01-01 [patent_title] => 'Interface structure for copper-copper peeling integrity' [patent_app_type] => utility [patent_app_number] => 12/633499 [patent_app_country] => US [patent_app_date] => 2009-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 3385 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12633499 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7763610 [patent_doc_number] => 08115293 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-02-14 [patent_title] => 'Integrated circuit packaging system with interconnect and method of manufacture thereof' [patent_app_type] => utility [patent_app_number] => 12/633789 [patent_app_country] => US [patent_app_date] => 2009-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 8776 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/115/08115293.pdf [firstpage_image] =>[orig_patent_app_number] => 12633789 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6208376 [patent_doc_number] => 20110133299 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-06-09 [patent_title] => 'Magnetic Tunnel Junction Device' [patent_app_type] => utility [patent_app_number] => 12/633264 [patent_app_country] => US [patent_app_date] => 2009-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6058 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0133/20110133299.pdf [firstpage_image] =>[orig_patent_app_number] => 12633264 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8528280 [patent_doc_number] => 08304853 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-11-06 [patent_title] => 'Fuse layout structure of semiconductor device' [patent_app_type] => utility [patent_app_number] => 12/631467 [patent_app_country] => US [patent_app_date] => 2009-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3110 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12631467 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6408855 [patent_doc_number] => 20100140589 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-06-10 [patent_title] => 'FERROELECTRIC TUNNEL FET SWITCH AND MEMORY' [patent_app_type] => utility [patent_app_number] => 12/631052 [patent_app_country] => US [patent_app_date] => 2009-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2841 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0140/20100140589.pdf [firstpage_image] =>[orig_patent_app_number] => 12631052 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8675949 [patent_doc_number] => 08384065 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-02-26 [patent_title] => 'Gate-all-around nanowire field effect transistors' [patent_app_type] => utility [patent_app_number] => 12/631199 [patent_app_country] => US [patent_app_date] => 2009-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 26 [patent_no_of_words] => 3465 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12631199 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8165554 [patent_doc_number] => 08173993 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-05-08 [patent_title] => 'Gate-all-around nanowire tunnel field effect transistors' [patent_app_type] => utility [patent_app_number] => 12/630942 [patent_app_country] => US [patent_app_date] => 2009-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 2713 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/173/08173993.pdf [firstpage_image] =>[orig_patent_app_number] => 12630942 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8363547 [patent_doc_number] => 08252612 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-08-28 [patent_title] => 'Organic EL display device and manufacturing method thereof' [patent_app_type] => utility [patent_app_number] => 12/630860 [patent_app_country] => US [patent_app_date] => 2009-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 5496 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12630860 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7801503 [patent_doc_number] => 08129775 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-03-06 [patent_title] => 'Semiconductor device and method of manufacturing the same' [patent_app_type] => utility [patent_app_number] => 12/630296 [patent_app_country] => US [patent_app_date] => 2009-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5217 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/129/08129775.pdf [firstpage_image] =>[orig_patent_app_number] => 12630296 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6286165 [patent_doc_number] => 20100237444 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-09-23 [patent_title] => 'Germanium Field Effect Transistors and Fabrication Thereof' [patent_app_type] => utility [patent_app_number] => 12/630652 [patent_app_country] => US [patent_app_date] => 2009-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5788 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0237/20100237444.pdf [firstpage_image] =>[orig_patent_app_number] => 12630652 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7730875 [patent_doc_number] => 08102022 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-01-24 [patent_title] => 'Semiconductor device manufacturing method and semiconductor device' [patent_app_type] => utility [patent_app_number] => 12/630337 [patent_app_country] => US [patent_app_date] => 2009-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 43 [patent_figures_cnt] => 43 [patent_no_of_words] => 16796 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/102/08102022.pdf [firstpage_image] =>[orig_patent_app_number] => 12630337 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4489128 [patent_doc_number] => 07884463 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-02-08 [patent_title] => 'Wiring board, semiconductor device and semiconductor element' [patent_app_type] => utility [patent_app_number] => 12/626037 [patent_app_country] => US [patent_app_date] => 2009-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 19 [patent_no_of_words] => 4486 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 231 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/884/07884463.pdf [firstpage_image] =>[orig_patent_app_number] => 12626037 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4485609 [patent_doc_number] => 07883936 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-02-08 [patent_title] => 'Multi layer low cost cavity substrate fabrication for PoP packages' [patent_app_type] => utility [patent_app_number] => 12/618859 [patent_app_country] => US [patent_app_date] => 2009-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 4660 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/883/07883936.pdf [firstpage_image] =>[orig_patent_app_number] => 12618859 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6544961 [patent_doc_number] => 20100044784 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-02-25 [patent_title] => 'Vertical Channel Fin Field-Effect Transistors Having Increased Source/Drain Contact Area and Methods for Fabricating the Same' [patent_app_type] => utility [patent_app_number] => 12/613025 [patent_app_country] => US [patent_app_date] => 2009-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 48 [patent_figures_cnt] => 48 [patent_no_of_words] => 18602 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0044/20100044784.pdf [firstpage_image] =>[orig_patent_app_number] => 12613025 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4538404 [patent_doc_number] => 07888802 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-02-15 [patent_title] => 'Bonding pad structure and manufacturing method thereof' [patent_app_type] => utility [patent_app_number] => 12/608018 [patent_app_country] => US [patent_app_date] => 2009-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 17 [patent_no_of_words] => 4492 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/888/07888802.pdf [firstpage_image] =>[orig_patent_app_number] => 12608018 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 73921 [patent_doc_number] => 07749791 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-07-06 [patent_title] => 'Sensor and method of manufacturing the same' [patent_app_type] => utility [patent_app_number] => 12/608979 [patent_app_country] => US [patent_app_date] => 2009-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 20 [patent_no_of_words] => 11552 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/749/07749791.pdf [firstpage_image] =>[orig_patent_app_number] => 12608979 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6336570 [patent_doc_number] => 20100019338 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-01-28 [patent_title] => 'STACK TYPE SEMICONDUCTOR CHIP PACKAGE HAVING DIFFERENT TYPE OF CHIPS AND FABRICATION METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 12/574906 [patent_app_country] => US [patent_app_date] => 2009-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5669 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0019/20100019338.pdf [firstpage_image] =>[orig_patent_app_number] => 12574906 [rel_patent_id] =>[rel_patent_doc_number] =>)