Roy Karl Potter

Array ( [id] => 583557 [patent_doc_number] => 07453111 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-11-18 [patent_title] => 'Phase-change memory device' [patent_app_type] => utility [patent_app_number] => 11/754437 [patent_app_country] => US [patent_app_date] => 2007-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 24 [patent_no_of_words] => 4456 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/453/07453111.pdf [firstpage_image] =>[orig_patent_app_number] => 11754437 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 360086 [patent_doc_number] => 07485965 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-02-03 [patent_title] => 'Through via in ultra high resistivity wafer and related methods' [patent_app_type] => utility [patent_app_number] => 11/753617 [patent_app_country] => US [patent_app_date] => 2007-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1745 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/485/07485965.pdf [firstpage_image] =>[orig_patent_app_number] => 11753617 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4810705 [patent_doc_number] => 20080191336 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-08-14 [patent_title] => 'Subminiature electronic device having hermetic cavity and method of manufacturing the same' [patent_app_type] => utility [patent_app_number] => 11/802695 [patent_app_country] => US [patent_app_date] => 2007-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7070 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0191/20080191336.pdf [firstpage_image] =>[orig_patent_app_number] => 11802695 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 367013 [patent_doc_number] => 07479698 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-01-20 [patent_title] => 'Bonding pad structure disposed in semiconductor device and related method' [patent_app_type] => utility [patent_app_number] => 11/753567 [patent_app_country] => US [patent_app_date] => 2007-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1905 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/479/07479698.pdf [firstpage_image] =>[orig_patent_app_number] => 11753567 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4789553 [patent_doc_number] => 20080290526 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-11-27 [patent_title] => 'Test patterns for detecting misalignment of through-wafer vias' [patent_app_type] => utility [patent_app_number] => 11/805767 [patent_app_country] => US [patent_app_date] => 2007-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3376 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0290/20080290526.pdf [firstpage_image] =>[orig_patent_app_number] => 11805767 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 196636 [patent_doc_number] => 07635914 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-12-22 [patent_title] => 'Multi layer low cost cavity substrate fabrication for pop packages' [patent_app_type] => utility [patent_app_number] => 11/804237 [patent_app_country] => US [patent_app_date] => 2007-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 4633 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/635/07635914.pdf [firstpage_image] =>[orig_patent_app_number] => 11804237 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4648808 [patent_doc_number] => 20080036063 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-02-14 [patent_title] => 'SEMICONDUCTOR PACKAGE HAVING FLEXIBLE LEAD CONNECTION PLATE FOR ELECTRICALLY CONNECTING BASE AND CHIP' [patent_app_type] => utility [patent_app_number] => 11/748577 [patent_app_country] => US [patent_app_date] => 2007-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 5916 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0036/20080036063.pdf [firstpage_image] =>[orig_patent_app_number] => 11748577 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4782560 [patent_doc_number] => 20080135889 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-06-12 [patent_title] => 'Structure and Method for Forming a Planar Schottky Contact' [patent_app_type] => utility [patent_app_number] => 11/747847 [patent_app_country] => US [patent_app_date] => 2007-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3136 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0135/20080135889.pdf [firstpage_image] =>[orig_patent_app_number] => 11747847 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 901005 [patent_doc_number] => 07339279 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-03-04 [patent_title] => 'Chip-size package structure and method of the same' [patent_app_type] => utility [patent_app_number] => 11/747417 [patent_app_country] => US [patent_app_date] => 2007-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 3590 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/339/07339279.pdf [firstpage_image] =>[orig_patent_app_number] => 11747417 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4863888 [patent_doc_number] => 20080142947 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-06-19 [patent_title] => 'CHIP PACKAGE AND METHOD OF MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 11/746064 [patent_app_country] => US [patent_app_date] => 2007-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4466 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0142/20080142947.pdf [firstpage_image] =>[orig_patent_app_number] => 11746064 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4795362 [patent_doc_number] => 20080006948 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-01-10 [patent_title] => 'Stack die packages' [patent_app_type] => utility [patent_app_number] => 11/801317 [patent_app_country] => US [patent_app_date] => 2007-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2699 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0006/20080006948.pdf [firstpage_image] =>[orig_patent_app_number] => 11801317 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5082925 [patent_doc_number] => 20070272976 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-11-29 [patent_title] => 'Power semiconductor module' [patent_app_type] => utility [patent_app_number] => 11/801357 [patent_app_country] => US [patent_app_date] => 2007-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1297 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0272/20070272976.pdf [firstpage_image] =>[orig_patent_app_number] => 11801357 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4958052 [patent_doc_number] => 20080272476 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-11-06 [patent_title] => 'Through-Hole Via On Saw Streets' [patent_app_type] => utility [patent_app_number] => 11/744657 [patent_app_country] => US [patent_app_date] => 2007-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 4817 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0272/20080272476.pdf [firstpage_image] =>[orig_patent_app_number] => 11744657 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 65067 [patent_doc_number] => 07759785 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-07-20 [patent_title] => 'Apparatus for packaging semiconductor devices, packaged semiconductor components, methods of manufacturing apparatus for packaging semiconductor devices, and methods of manufacturing semiconductor components' [patent_app_type] => utility [patent_app_number] => 11/742297 [patent_app_country] => US [patent_app_date] => 2007-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 15 [patent_no_of_words] => 4976 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/759/07759785.pdf [firstpage_image] =>[orig_patent_app_number] => 11742297 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 152396 [patent_doc_number] => 07683464 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-03-23 [patent_title] => 'Semiconductor package having dimpled plate interconnections' [patent_app_type] => utility [patent_app_number] => 11/799467 [patent_app_country] => US [patent_app_date] => 2007-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 22 [patent_no_of_words] => 3607 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/683/07683464.pdf [firstpage_image] =>[orig_patent_app_number] => 11799467 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4856549 [patent_doc_number] => 20080265399 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-30 [patent_title] => 'Low-cost and ultra-fine integrated circuit packaging technique' [patent_app_type] => utility [patent_app_number] => 11/796297 [patent_app_country] => US [patent_app_date] => 2007-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 2774 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0265/20080265399.pdf [firstpage_image] =>[orig_patent_app_number] => 11796297 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 217013 [patent_doc_number] => 07611923 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-11-03 [patent_title] => 'Method and apparatus for forming stacked die and substrate structures for increased packing density' [patent_app_type] => utility [patent_app_number] => 11/740962 [patent_app_country] => US [patent_app_date] => 2007-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 11 [patent_no_of_words] => 3031 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/611/07611923.pdf [firstpage_image] =>[orig_patent_app_number] => 11740962 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4856389 [patent_doc_number] => 20080265239 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-30 [patent_title] => 'INTEGRATED CIRCUIT INCLUDING SPACER MATERIAL LAYER' [patent_app_type] => utility [patent_app_number] => 11/740657 [patent_app_country] => US [patent_app_date] => 2007-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4769 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0265/20080265239.pdf [firstpage_image] =>[orig_patent_app_number] => 11740657 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4795333 [patent_doc_number] => 20080006919 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-01-10 [patent_title] => 'Flip chip package and method of fabricating the same' [patent_app_type] => utility [patent_app_number] => 11/790177 [patent_app_country] => US [patent_app_date] => 2007-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3248 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0006/20080006919.pdf [firstpage_image] =>[orig_patent_app_number] => 11790177 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4553389 [patent_doc_number] => 07960839 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-06-14 [patent_title] => 'Semiconductor interconnection line and method of forming the same' [patent_app_type] => utility [patent_app_number] => 11/788794 [patent_app_country] => US [patent_app_date] => 2007-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 2218 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/960/07960839.pdf [firstpage_image] =>[orig_patent_app_number] => 11788794 [rel_patent_id] =>[rel_patent_doc_number] =>)