
Roy Karl Potter
Examiner (ID: 13991, Phone: (571)272-1842 , Office: P/2822 )
| Most Active Art Unit | 2822 |
| Art Unit(s) | 2822, 2508, 2811, 3621 |
| Total Applications | 2584 |
| Issued Applications | 2409 |
| Pending Applications | 46 |
| Abandoned Applications | 141 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 311439
[patent_doc_number] => 07528471
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-05-05
[patent_title] => 'Integrated circuit incorporating wire bond inductance'
[patent_app_type] => utility
[patent_app_number] => 11/548516
[patent_app_country] => US
[patent_app_date] => 2006-10-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 6
[patent_no_of_words] => 2126
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/528/07528471.pdf
[firstpage_image] =>[orig_patent_app_number] => 11548516
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/548516 | Integrated circuit incorporating wire bond inductance | Oct 10, 2006 | Issued |
Array
(
[id] => 322992
[patent_doc_number] => 07518225
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-04-14
[patent_title] => 'Chip system architecture for performance enhancement, power reduction and cost reduction'
[patent_app_type] => utility
[patent_app_number] => 11/538567
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[firstpage_image] =>[orig_patent_app_number] => 11538567
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/538567 | Chip system architecture for performance enhancement, power reduction and cost reduction | Oct 3, 2006 | Issued |
Array
(
[id] => 814049
[patent_doc_number] => 07414324
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-08-19
[patent_title] => 'Wafer structure with mirror shot'
[patent_app_type] => utility
[patent_app_number] => 11/543187
[patent_app_country] => US
[patent_app_date] => 2006-10-04
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[pdf_file] => patents/07/414/07414324.pdf
[firstpage_image] =>[orig_patent_app_number] => 11543187
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/543187 | Wafer structure with mirror shot | Oct 3, 2006 | Issued |
Array
(
[id] => 415179
[patent_doc_number] => 07279360
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-10-09
[patent_title] => 'Semiconductor device and method of packaging the same'
[patent_app_type] => utility
[patent_app_number] => 11/536270
[patent_app_country] => US
[patent_app_date] => 2006-09-28
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/07/279/07279360.pdf
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/536270 | Semiconductor device and method of packaging the same | Sep 27, 2006 | Issued |
Array
(
[id] => 5239799
[patent_doc_number] => 20070018290
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-01-25
[patent_title] => 'LARGE DIE PACKAGE STRUCTURES AND FABRICATION METHOD THEREFOR'
[patent_app_type] => utility
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/536544 | Large die package structures and fabrication method therefor | Sep 27, 2006 | Issued |
Array
(
[id] => 256728
[patent_doc_number] => 07576405
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-08-18
[patent_title] => 'Semiconductor integrated circuit for reducing leak current through MOS transistors'
[patent_app_type] => utility
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[pdf_file] => patents/07/576/07576405.pdf
[firstpage_image] =>[orig_patent_app_number] => 11526577
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/526577 | Semiconductor integrated circuit for reducing leak current through MOS transistors | Sep 25, 2006 | Issued |
Array
(
[id] => 4743413
[patent_doc_number] => 20080088014
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-04-17
[patent_title] => 'STACKED IMAGER PACKAGE'
[patent_app_type] => utility
[patent_app_number] => 11/528227
[patent_app_country] => US
[patent_app_date] => 2006-09-26
[patent_effective_date] => 0000-00-00
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[pdf_file] => publications/A1/0088/20080088014.pdf
[firstpage_image] =>[orig_patent_app_number] => 11528227
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/528227 | Stacked imager package | Sep 25, 2006 | Issued |
Array
(
[id] => 852915
[patent_doc_number] => 07378298
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-05-27
[patent_title] => 'Method of making stacked die package'
[patent_app_type] => utility
[patent_app_number] => 11/524457
[patent_app_country] => US
[patent_app_date] => 2006-09-20
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/07/378/07378298.pdf
[firstpage_image] =>[orig_patent_app_number] => 11524457
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/524457 | Method of making stacked die package | Sep 19, 2006 | Issued |
Array
(
[id] => 5239829
[patent_doc_number] => 20070018320
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-01-25
[patent_title] => 'Semiconductor chip production method, semiconductor device production method, semiconductor chip, and semiconductor device'
[patent_app_type] => utility
[patent_app_number] => 11/518889
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/518889 | Semiconductor chip production method, semiconductor device production method, semiconductor chip, and semiconductor device | Sep 11, 2006 | Issued |
Array
(
[id] => 4701911
[patent_doc_number] => 20080061433
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[patent_title] => 'Methods and substrates to connect an electrical member to a substrate to form a bonded structure'
[patent_app_type] => utility
[patent_app_number] => 11/518837
[patent_app_country] => US
[patent_app_date] => 2006-09-11
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/518837 | Methods and substrates to connect an electrical member to a substrate to form a bonded structure | Sep 10, 2006 | Abandoned |
Array
(
[id] => 449859
[patent_doc_number] => 07250677
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[patent_title] => 'Die package structure'
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Array
(
[id] => 5141990
[patent_doc_number] => 20070004206
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[patent_title] => 'IMPROVED HDP-BASED ILD CAPPING LAYER'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/467593 | HDP-based ILD capping layer | Aug 27, 2006 | Issued |
Array
(
[id] => 4733898
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[patent_title] => 'Superjunction trench device and method'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/510547 | Superjunction trench device and method | Aug 24, 2006 | Issued |
Array
(
[id] => 887882
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[patent_title] => 'Semiconductor packages and methods of manufacturing thereof'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/467053 | Semiconductor packages and methods of manufacturing thereof | Aug 23, 2006 | Issued |
Array
(
[id] => 5567393
[patent_doc_number] => 20090250771
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[patent_issue_date] => 2009-10-08
[patent_title] => 'Mosfet and production method of semiconductor device'
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Array
(
[id] => 4999934
[patent_doc_number] => 20070042568
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[patent_title] => 'SEMICONDUCTOR DEVICE WITH A THINNED SEMICONDUCTOR CHIP AND METHOD FOR PRODUCING THE THINNED SEMICONDUCTOR CHIP'
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Array
(
[id] => 338375
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Array
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Array
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Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/462537 | Integrated circuit package-in-package system | Aug 3, 2006 | Issued |