Search

Roy Karl Potter

Examiner (ID: 13991, Phone: (571)272-1842 , Office: P/2822 )

Most Active Art Unit
2822
Art Unit(s)
2822, 2508, 2811, 3621
Total Applications
2584
Issued Applications
2409
Pending Applications
46
Abandoned Applications
141

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 311439 [patent_doc_number] => 07528471 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-05-05 [patent_title] => 'Integrated circuit incorporating wire bond inductance' [patent_app_type] => utility [patent_app_number] => 11/548516 [patent_app_country] => US [patent_app_date] => 2006-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 2126 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/528/07528471.pdf [firstpage_image] =>[orig_patent_app_number] => 11548516 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/548516
Integrated circuit incorporating wire bond inductance Oct 10, 2006 Issued
Array ( [id] => 322992 [patent_doc_number] => 07518225 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-04-14 [patent_title] => 'Chip system architecture for performance enhancement, power reduction and cost reduction' [patent_app_type] => utility [patent_app_number] => 11/538567 [patent_app_country] => US [patent_app_date] => 2006-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6600 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/518/07518225.pdf [firstpage_image] =>[orig_patent_app_number] => 11538567 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/538567
Chip system architecture for performance enhancement, power reduction and cost reduction Oct 3, 2006 Issued
Array ( [id] => 814049 [patent_doc_number] => 07414324 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-08-19 [patent_title] => 'Wafer structure with mirror shot' [patent_app_type] => utility [patent_app_number] => 11/543187 [patent_app_country] => US [patent_app_date] => 2006-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1799 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 39 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/414/07414324.pdf [firstpage_image] =>[orig_patent_app_number] => 11543187 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/543187
Wafer structure with mirror shot Oct 3, 2006 Issued
Array ( [id] => 415179 [patent_doc_number] => 07279360 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-10-09 [patent_title] => 'Semiconductor device and method of packaging the same' [patent_app_type] => utility [patent_app_number] => 11/536270 [patent_app_country] => US [patent_app_date] => 2006-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 3848 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/279/07279360.pdf [firstpage_image] =>[orig_patent_app_number] => 11536270 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/536270
Semiconductor device and method of packaging the same Sep 27, 2006 Issued
Array ( [id] => 5239799 [patent_doc_number] => 20070018290 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-01-25 [patent_title] => 'LARGE DIE PACKAGE STRUCTURES AND FABRICATION METHOD THEREFOR' [patent_app_type] => utility [patent_app_number] => 11/536544 [patent_app_country] => US [patent_app_date] => 2006-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3604 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0018/20070018290.pdf [firstpage_image] =>[orig_patent_app_number] => 11536544 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/536544
Large die package structures and fabrication method therefor Sep 27, 2006 Issued
Array ( [id] => 256728 [patent_doc_number] => 07576405 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-08-18 [patent_title] => 'Semiconductor integrated circuit for reducing leak current through MOS transistors' [patent_app_type] => utility [patent_app_number] => 11/526577 [patent_app_country] => US [patent_app_date] => 2006-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 22 [patent_no_of_words] => 6023 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 212 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/576/07576405.pdf [firstpage_image] =>[orig_patent_app_number] => 11526577 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/526577
Semiconductor integrated circuit for reducing leak current through MOS transistors Sep 25, 2006 Issued
Array ( [id] => 4743413 [patent_doc_number] => 20080088014 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-04-17 [patent_title] => 'STACKED IMAGER PACKAGE' [patent_app_type] => utility [patent_app_number] => 11/528227 [patent_app_country] => US [patent_app_date] => 2006-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2934 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0088/20080088014.pdf [firstpage_image] =>[orig_patent_app_number] => 11528227 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/528227
Stacked imager package Sep 25, 2006 Issued
Array ( [id] => 852915 [patent_doc_number] => 07378298 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-05-27 [patent_title] => 'Method of making stacked die package' [patent_app_type] => utility [patent_app_number] => 11/524457 [patent_app_country] => US [patent_app_date] => 2006-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 3734 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/378/07378298.pdf [firstpage_image] =>[orig_patent_app_number] => 11524457 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/524457
Method of making stacked die package Sep 19, 2006 Issued
Array ( [id] => 5239829 [patent_doc_number] => 20070018320 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-01-25 [patent_title] => 'Semiconductor chip production method, semiconductor device production method, semiconductor chip, and semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/518889 [patent_app_country] => US [patent_app_date] => 2006-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 17414 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0018/20070018320.pdf [firstpage_image] =>[orig_patent_app_number] => 11518889 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/518889
Semiconductor chip production method, semiconductor device production method, semiconductor chip, and semiconductor device Sep 11, 2006 Issued
Array ( [id] => 4701911 [patent_doc_number] => 20080061433 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-03-13 [patent_title] => 'Methods and substrates to connect an electrical member to a substrate to form a bonded structure' [patent_app_type] => utility [patent_app_number] => 11/518837 [patent_app_country] => US [patent_app_date] => 2006-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6082 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0061/20080061433.pdf [firstpage_image] =>[orig_patent_app_number] => 11518837 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/518837
Methods and substrates to connect an electrical member to a substrate to form a bonded structure Sep 10, 2006 Abandoned
Array ( [id] => 449859 [patent_doc_number] => 07250677 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-07-31 [patent_title] => 'Die package structure' [patent_app_type] => utility [patent_app_number] => 11/514827 [patent_app_country] => US [patent_app_date] => 2006-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 1702 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/250/07250677.pdf [firstpage_image] =>[orig_patent_app_number] => 11514827 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/514827
Die package structure Sep 4, 2006 Issued
Array ( [id] => 5141990 [patent_doc_number] => 20070004206 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-01-04 [patent_title] => 'IMPROVED HDP-BASED ILD CAPPING LAYER' [patent_app_type] => utility [patent_app_number] => 11/467593 [patent_app_country] => US [patent_app_date] => 2006-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 7460 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0004/20070004206.pdf [firstpage_image] =>[orig_patent_app_number] => 11467593 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/467593
HDP-based ILD capping layer Aug 27, 2006 Issued
Array ( [id] => 4733898 [patent_doc_number] => 20080050877 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-02-28 [patent_title] => 'Superjunction trench device and method' [patent_app_type] => utility [patent_app_number] => 11/510547 [patent_app_country] => US [patent_app_date] => 2006-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 9991 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0050/20080050877.pdf [firstpage_image] =>[orig_patent_app_number] => 11510547 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/510547
Superjunction trench device and method Aug 24, 2006 Issued
Array ( [id] => 887882 [patent_doc_number] => 07348218 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-03-25 [patent_title] => 'Semiconductor packages and methods of manufacturing thereof' [patent_app_type] => utility [patent_app_number] => 11/467053 [patent_app_country] => US [patent_app_date] => 2006-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2857 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/348/07348218.pdf [firstpage_image] =>[orig_patent_app_number] => 11467053 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/467053
Semiconductor packages and methods of manufacturing thereof Aug 23, 2006 Issued
Array ( [id] => 5567393 [patent_doc_number] => 20090250771 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-10-08 [patent_title] => 'Mosfet and production method of semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/990747 [patent_app_country] => US [patent_app_date] => 2006-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 9504 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0250/20090250771.pdf [firstpage_image] =>[orig_patent_app_number] => 11990747 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/990747
MOSFET and production method of semiconductor device Aug 21, 2006 Issued
Array ( [id] => 4999934 [patent_doc_number] => 20070042568 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-02-22 [patent_title] => 'SEMICONDUCTOR DEVICE WITH A THINNED SEMICONDUCTOR CHIP AND METHOD FOR PRODUCING THE THINNED SEMICONDUCTOR CHIP' [patent_app_type] => utility [patent_app_number] => 11/465547 [patent_app_country] => US [patent_app_date] => 2006-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4862 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0042/20070042568.pdf [firstpage_image] =>[orig_patent_app_number] => 11465547 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/465547
Semiconductor device with a thinned semiconductor chip and method for producing the thinned semiconductor chip Aug 17, 2006 Issued
Array ( [id] => 338375 [patent_doc_number] => 07504720 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-03-17 [patent_title] => 'Semiconductor unit, and power conversion system and on-vehicle electrical system using the same' [patent_app_type] => utility [patent_app_number] => 11/505467 [patent_app_country] => US [patent_app_date] => 2006-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 34 [patent_no_of_words] => 22844 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/504/07504720.pdf [firstpage_image] =>[orig_patent_app_number] => 11505467 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/505467
Semiconductor unit, and power conversion system and on-vehicle electrical system using the same Aug 16, 2006 Issued
Array ( [id] => 341890 [patent_doc_number] => 07501648 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-03-10 [patent_title] => 'Phase change materials and associated memory devices' [patent_app_type] => utility [patent_app_number] => 11/465077 [patent_app_country] => US [patent_app_date] => 2006-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 6070 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/501/07501648.pdf [firstpage_image] =>[orig_patent_app_number] => 11465077 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/465077
Phase change materials and associated memory devices Aug 15, 2006 Issued
Array ( [id] => 900984 [patent_doc_number] => 07339268 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-03-04 [patent_title] => 'Thermal dissipation from a flip chip through an aperture in a flex cable' [patent_app_type] => utility [patent_app_number] => 11/500567 [patent_app_country] => US [patent_app_date] => 2006-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 1824 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/339/07339268.pdf [firstpage_image] =>[orig_patent_app_number] => 11500567 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/500567
Thermal dissipation from a flip chip through an aperture in a flex cable Aug 7, 2006 Issued
Array ( [id] => 591508 [patent_doc_number] => 07439620 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-10-21 [patent_title] => 'Integrated circuit package-in-package system' [patent_app_type] => utility [patent_app_number] => 11/462537 [patent_app_country] => US [patent_app_date] => 2006-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 16 [patent_no_of_words] => 4673 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/439/07439620.pdf [firstpage_image] =>[orig_patent_app_number] => 11462537 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/462537
Integrated circuit package-in-package system Aug 3, 2006 Issued
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