
Roy Karl Potter
Examiner (ID: 13991, Phone: (571)272-1842 , Office: P/2822 )
| Most Active Art Unit | 2822 |
| Art Unit(s) | 2822, 2508, 2811, 3621 |
| Total Applications | 2584 |
| Issued Applications | 2409 |
| Pending Applications | 46 |
| Abandoned Applications | 141 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 4723864
[patent_doc_number] => 20080203405
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-08-28
[patent_title] => 'Method for Preparing an Electric Circuit Comprising Multiple Leds'
[patent_app_type] => utility
[patent_app_number] => 11/997932
[patent_app_country] => US
[patent_app_date] => 2006-08-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 6675
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 10
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0203/20080203405.pdf
[firstpage_image] =>[orig_patent_app_number] => 11997932
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/997932 | Method for Preparing an Electric Circuit Comprising Multiple Leds | Aug 3, 2006 | Abandoned |
Array
(
[id] => 573877
[patent_doc_number] => 07459393
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-12-02
[patent_title] => 'Method for fabricating semiconductor components with thinned substrate, circuit side contacts, conductive vias and backside contacts'
[patent_app_type] => utility
[patent_app_number] => 11/497699
[patent_app_country] => US
[patent_app_date] => 2006-08-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 27
[patent_figures_cnt] => 62
[patent_no_of_words] => 14743
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 8
[patent_words_short_claim] => 80
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/459/07459393.pdf
[firstpage_image] =>[orig_patent_app_number] => 11497699
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/497699 | Method for fabricating semiconductor components with thinned substrate, circuit side contacts, conductive vias and backside contacts | Aug 1, 2006 | Issued |
Array
(
[id] => 447746
[patent_doc_number] => 07253515
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-08-07
[patent_title] => 'Semiconductor package featuring metal lid member'
[patent_app_type] => utility
[patent_app_number] => 11/495737
[patent_app_country] => US
[patent_app_date] => 2006-07-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 13
[patent_no_of_words] => 6257
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 2
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[patent_maintenance] => 1
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/253/07253515.pdf
[firstpage_image] =>[orig_patent_app_number] => 11495737
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/495737 | Semiconductor package featuring metal lid member | Jul 30, 2006 | Issued |
Array
(
[id] => 5884284
[patent_doc_number] => 20060273459
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-12-07
[patent_title] => 'Semiconductor processing methods of forming contact openings, methods of forming electrical connections and interconnections, and integrated circuitry'
[patent_app_type] => utility
[patent_app_number] => 11/496843
[patent_app_country] => US
[patent_app_date] => 2006-07-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 2336
[patent_no_of_claims] => 4
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[patent_words_short_claim] => 0
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0273/20060273459.pdf
[firstpage_image] =>[orig_patent_app_number] => 11496843
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/496843 | Semiconductor processing methods of forming contact openings, methods of forming electrical connections and interconnections, and integrated circuitry | Jul 30, 2006 | Abandoned |
Array
(
[id] => 4907228
[patent_doc_number] => 20080017994
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-01-24
[patent_title] => 'LEADED STACKED PACKAGES HAVING ELEVATED DIE PADDLE'
[patent_app_type] => utility
[patent_app_number] => 11/459557
[patent_app_country] => US
[patent_app_date] => 2006-07-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 3667
[patent_no_of_claims] => 24
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[patent_maintenance] => 1
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0017/20080017994.pdf
[firstpage_image] =>[orig_patent_app_number] => 11459557
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/459557 | Leaded stacked packages having elevated die paddle | Jul 23, 2006 | Issued |
Array
(
[id] => 830105
[patent_doc_number] => 07399658
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-07-15
[patent_title] => 'Pre-molded leadframe and method therefor'
[patent_app_type] => utility
[patent_app_number] => 11/459317
[patent_app_country] => US
[patent_app_date] => 2006-07-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
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[patent_no_of_words] => 5780
[patent_no_of_claims] => 20
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/399/07399658.pdf
[firstpage_image] =>[orig_patent_app_number] => 11459317
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/459317 | Pre-molded leadframe and method therefor | Jul 20, 2006 | Issued |
Array
(
[id] => 873322
[patent_doc_number] => 07361981
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-04-22
[patent_title] => 'Pad layout'
[patent_app_type] => utility
[patent_app_number] => 11/458787
[patent_app_country] => US
[patent_app_date] => 2006-07-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 10
[patent_no_of_words] => 3074
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 109
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/361/07361981.pdf
[firstpage_image] =>[orig_patent_app_number] => 11458787
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/458787 | Pad layout | Jul 19, 2006 | Issued |
Array
(
[id] => 243684
[patent_doc_number] => 07589421
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-09-15
[patent_title] => 'Heat-radiating semiconductor chip, tape wiring substrate and tape package using the same'
[patent_app_type] => utility
[patent_app_number] => 11/488057
[patent_app_country] => US
[patent_app_date] => 2006-07-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 15
[patent_no_of_words] => 4624
[patent_no_of_claims] => 34
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 43
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/589/07589421.pdf
[firstpage_image] =>[orig_patent_app_number] => 11488057
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/488057 | Heat-radiating semiconductor chip, tape wiring substrate and tape package using the same | Jul 17, 2006 | Issued |
Array
(
[id] => 830493
[patent_doc_number] => 07400048
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-07-15
[patent_title] => 'Void-free circuit board and semiconductor package having the same'
[patent_app_type] => utility
[patent_app_number] => 11/457767
[patent_app_country] => US
[patent_app_date] => 2006-07-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
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[patent_no_of_words] => 3924
[patent_no_of_claims] => 26
[patent_no_of_ind_claims] => 2
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[patent_maintenance] => 1
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/400/07400048.pdf
[firstpage_image] =>[orig_patent_app_number] => 11457767
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/457767 | Void-free circuit board and semiconductor package having the same | Jul 13, 2006 | Issued |
Array
(
[id] => 5605654
[patent_doc_number] => 20060267170
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-11-30
[patent_title] => 'Integrated circuit package with air gap'
[patent_app_type] => utility
[patent_app_number] => 11/487077
[patent_app_country] => US
[patent_app_date] => 2006-07-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 27
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[patent_no_of_words] => 15123
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[pdf_file] => publications/A1/0267/20060267170.pdf
[firstpage_image] =>[orig_patent_app_number] => 11487077
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/487077 | Integrated circuit package with air gap | Jul 13, 2006 | Issued |
Array
(
[id] => 5060448
[patent_doc_number] => 20070222085
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-09-27
[patent_title] => 'Semiconductor device and fabrication process thereof'
[patent_app_type] => utility
[patent_app_number] => 11/483527
[patent_app_country] => US
[patent_app_date] => 2006-07-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
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[patent_no_of_words] => 3898
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[pdf_file] => publications/A1/0222/20070222085.pdf
[firstpage_image] =>[orig_patent_app_number] => 11483527
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/483527 | Semiconductor device and fabrication process thereof | Jul 10, 2006 | Issued |
Array
(
[id] => 282202
[patent_doc_number] => 07554203
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-06-30
[patent_title] => 'Electronic assembly with stacked IC\'s using two or more different connection technologies and methods of manufacture'
[patent_app_type] => utility
[patent_app_number] => 11/427917
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[pdf_file] => patents/07/554/07554203.pdf
[firstpage_image] =>[orig_patent_app_number] => 11427917
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/427917 | Electronic assembly with stacked IC's using two or more different connection technologies and methods of manufacture | Jun 29, 2006 | Issued |
Array
(
[id] => 380336
[patent_doc_number] => 07309912
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2007-12-18
[patent_title] => 'On-package edge-mount power decoupling and implementation with novel substrate design for FPGA and ASIC devices'
[patent_app_type] => utility
[patent_app_number] => 11/478017
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[pdf_file] => patents/07/309/07309912.pdf
[firstpage_image] =>[orig_patent_app_number] => 11478017
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/478017 | On-package edge-mount power decoupling and implementation with novel substrate design for FPGA and ASIC devices | Jun 27, 2006 | Issued |
Array
(
[id] => 5834903
[patent_doc_number] => 20060246734
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-11-02
[patent_title] => 'Methods of forming patterned photoresist layers over semiconductor substrates'
[patent_app_type] => utility
[patent_app_number] => 11/477287
[patent_app_country] => US
[patent_app_date] => 2006-06-28
[patent_effective_date] => 0000-00-00
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[pdf_file] => publications/A1/0246/20060246734.pdf
[firstpage_image] =>[orig_patent_app_number] => 11477287
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/477287 | Methods of forming patterned photoresist layers over semiconductor substrates | Jun 27, 2006 | Issued |
Array
(
[id] => 267430
[patent_doc_number] => 07566956
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[patent_kind] => B2
[patent_issue_date] => 2009-07-28
[patent_title] => 'Semiconductor composite device and method of manufacturing the same'
[patent_app_type] => utility
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[firstpage_image] =>[orig_patent_app_number] => 11425077
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/425077 | Semiconductor composite device and method of manufacturing the same | Jun 18, 2006 | Issued |
Array
(
[id] => 591433
[patent_doc_number] => 07439610
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-10-21
[patent_title] => 'High power shunt switch with high isolation and ease of assembly'
[patent_app_type] => utility
[patent_app_number] => 11/455067
[patent_app_country] => US
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[pdf_file] => patents/07/439/07439610.pdf
[firstpage_image] =>[orig_patent_app_number] => 11455067
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/455067 | High power shunt switch with high isolation and ease of assembly | Jun 15, 2006 | Issued |
Array
(
[id] => 5139092
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[patent_title] => 'Semiconductor device'
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[firstpage_image] =>[orig_patent_app_number] => 11452957
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/452957 | Semiconductor device | Jun 14, 2006 | Issued |
Array
(
[id] => 221344
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/451318 | Semiconductor device and method of manufacturing semiconductor device | Jun 12, 2006 | Issued |
Array
(
[id] => 5640513
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[patent_title] => 'LAMINATED SEMICONDUCTOR PACKAGE'
[patent_app_type] => utility
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[firstpage_image] =>[orig_patent_app_number] => 11423597
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/423597 | Laminated semiconductor package | Jun 11, 2006 | Issued |
Array
(
[id] => 800321
[patent_doc_number] => 07425463
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[patent_kind] => B2
[patent_issue_date] => 2008-09-16
[patent_title] => 'Stacked die package for peripheral and center device pad layout device'
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/425/07425463.pdf
[firstpage_image] =>[orig_patent_app_number] => 11450485
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/450485 | Stacked die package for peripheral and center device pad layout device | Jun 8, 2006 | Issued |