Search

Roy Karl Potter

Examiner (ID: 13991, Phone: (571)272-1842 , Office: P/2822 )

Most Active Art Unit
2822
Art Unit(s)
2822, 2508, 2811, 3621
Total Applications
2584
Issued Applications
2409
Pending Applications
46
Abandoned Applications
141

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 9962255 [patent_doc_number] => RE045481 [patent_country] => US [patent_kind] => E1 [patent_issue_date] => 2015-04-21 [patent_title] => 'Interconnector line of thin film, sputter target for forming the wiring film and electronic component using the same' [patent_app_type] => reissue [patent_app_number] => 11/386117 [patent_app_country] => US [patent_app_date] => 2006-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 11369 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11386117 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/386117
Interconnector line of thin film, sputter target for forming the wiring film and electronic component using the same Mar 21, 2006 Issued
11/386116 Interconnector line of thin film, sputter target for forming the wiring film and electronic component using the same Mar 21, 2006 Abandoned
Array ( [id] => 5874481 [patent_doc_number] => 20060166400 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-07-27 [patent_title] => 'Electronic assembly with integrated IO and power contacts' [patent_app_type] => utility [patent_app_number] => 11/384964 [patent_app_country] => US [patent_app_date] => 2006-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2459 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0166/20060166400.pdf [firstpage_image] =>[orig_patent_app_number] => 11384964 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/384964
Electronic assembly with integrated IO and power contacts Mar 19, 2006 Issued
Array ( [id] => 5593941 [patent_doc_number] => 20060157857 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-07-20 [patent_title] => 'Metal capped copper interconnect' [patent_app_type] => utility [patent_app_number] => 11/376199 [patent_app_country] => US [patent_app_date] => 2006-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5814 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0157/20060157857.pdf [firstpage_image] =>[orig_patent_app_number] => 11376199 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/376199
Metal capped copper interconnect Mar 15, 2006 Issued
Array ( [id] => 5869119 [patent_doc_number] => 20060163736 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-07-27 [patent_title] => 'Interconnections having double capping layer and method for forming the same' [patent_app_type] => utility [patent_app_number] => 11/367790 [patent_app_country] => US [patent_app_date] => 2006-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3543 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0163/20060163736.pdf [firstpage_image] =>[orig_patent_app_number] => 11367790 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/367790
Interconnections having double capping layer and method for forming the same Mar 2, 2006 Issued
Array ( [id] => 5038138 [patent_doc_number] => 20070090420 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-04-26 [patent_title] => 'PIXEL ARRAY' [patent_app_type] => utility [patent_app_number] => 11/358967 [patent_app_country] => US [patent_app_date] => 2006-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 5447 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0090/20070090420.pdf [firstpage_image] =>[orig_patent_app_number] => 11358967 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/358967
Pixel array Feb 20, 2006 Issued
Array ( [id] => 5110499 [patent_doc_number] => 20070194414 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-08-23 [patent_title] => 'Method for providing and removing discharging interconnect for chip-on-glass output leads and structures thereof' [patent_app_type] => utility [patent_app_number] => 11/358997 [patent_app_country] => US [patent_app_date] => 2006-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 9165 [patent_no_of_claims] => 42 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0194/20070194414.pdf [firstpage_image] =>[orig_patent_app_number] => 11358997 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/358997
Method for providing and removing discharging interconnect for chip-on-glass output leads and structures thereof Feb 20, 2006 Issued
Array ( [id] => 5652863 [patent_doc_number] => 20060138598 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-06-29 [patent_title] => 'Localized slots for stress relieve in copper' [patent_app_type] => utility [patent_app_number] => 11/357696 [patent_app_country] => US [patent_app_date] => 2006-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3781 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0138/20060138598.pdf [firstpage_image] =>[orig_patent_app_number] => 11357696 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/357696
Localized slots for stress relieve in copper Feb 16, 2006 Issued
Array ( [id] => 5869118 [patent_doc_number] => 20060163735 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-07-27 [patent_title] => 'Damascene process at semiconductor substrate level' [patent_app_type] => utility [patent_app_number] => 11/357697 [patent_app_country] => US [patent_app_date] => 2006-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2898 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0163/20060163735.pdf [firstpage_image] =>[orig_patent_app_number] => 11357697 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/357697
Damascene process at semiconductor substrate level Feb 16, 2006 Issued
Array ( [id] => 5066713 [patent_doc_number] => 20070187814 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-08-16 [patent_title] => 'System and method for routing supply voltages or other signals between side-by-side die and a lead frame for system in a package (SIP) devices' [patent_app_type] => utility [patent_app_number] => 11/352167 [patent_app_country] => US [patent_app_date] => 2006-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5828 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0187/20070187814.pdf [firstpage_image] =>[orig_patent_app_number] => 11352167 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/352167
System and method for routing supply voltages or other signals between side-by-side die and a lead frame for system in a package (SIP) devices Feb 9, 2006 Issued
Array ( [id] => 5703239 [patent_doc_number] => 20060192286 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-08-31 [patent_title] => 'Semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/341067 [patent_app_country] => US [patent_app_date] => 2006-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 13368 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0192/20060192286.pdf [firstpage_image] =>[orig_patent_app_number] => 11341067 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/341067
Semiconductor device Jan 26, 2006 Issued
Array ( [id] => 419093 [patent_doc_number] => 07276768 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-10-02 [patent_title] => 'Semiconductor structures for latch-up suppression and methods of forming such semiconductor structures' [patent_app_type] => utility [patent_app_number] => 11/340737 [patent_app_country] => US [patent_app_date] => 2006-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 19 [patent_no_of_words] => 8855 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/276/07276768.pdf [firstpage_image] =>[orig_patent_app_number] => 11340737 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/340737
Semiconductor structures for latch-up suppression and methods of forming such semiconductor structures Jan 25, 2006 Issued
Array ( [id] => 881242 [patent_doc_number] => 07355290 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-04-08 [patent_title] => 'Interposer and method for fabricating the same' [patent_app_type] => utility [patent_app_number] => 11/338857 [patent_app_country] => US [patent_app_date] => 2006-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 87 [patent_figures_cnt] => 186 [patent_no_of_words] => 43950 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/355/07355290.pdf [firstpage_image] =>[orig_patent_app_number] => 11338857 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/338857
Interposer and method for fabricating the same Jan 24, 2006 Issued
Array ( [id] => 322987 [patent_doc_number] => 07518220 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-04-14 [patent_title] => 'Substrate for an FBGA semiconductor component' [patent_app_type] => utility [patent_app_number] => 11/338867 [patent_app_country] => US [patent_app_date] => 2006-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 2880 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/518/07518220.pdf [firstpage_image] =>[orig_patent_app_number] => 11338867 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/338867
Substrate for an FBGA semiconductor component Jan 23, 2006 Issued
Array ( [id] => 5838262 [patent_doc_number] => 20060118920 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-06-08 [patent_title] => 'Method of wet etching vias and articles formed thereby' [patent_app_type] => utility [patent_app_number] => 11/337249 [patent_app_country] => US [patent_app_date] => 2006-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2171 [patent_no_of_claims] => 50 [patent_no_of_ind_claims] => 25 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0118/20060118920.pdf [firstpage_image] =>[orig_patent_app_number] => 11337249 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/337249
Method of wet etching vias and articles formed thereby Jan 22, 2006 Issued
Array ( [id] => 480158 [patent_doc_number] => 07224051 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-05-29 [patent_title] => 'Semiconductor component having plate and stacked dice' [patent_app_type] => utility [patent_app_number] => 11/333662 [patent_app_country] => US [patent_app_date] => 2006-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 62 [patent_no_of_words] => 14705 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/224/07224051.pdf [firstpage_image] =>[orig_patent_app_number] => 11333662 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/333662
Semiconductor component having plate and stacked dice Jan 16, 2006 Issued
Array ( [id] => 4564608 [patent_doc_number] => 07838997 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-11-23 [patent_title] => 'Remote chip attachment' [patent_app_type] => utility [patent_app_number] => 11/329557 [patent_app_country] => US [patent_app_date] => 2006-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 122 [patent_figures_cnt] => 276 [patent_no_of_words] => 48088 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/838/07838997.pdf [firstpage_image] =>[orig_patent_app_number] => 11329557 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/329557
Remote chip attachment Jan 9, 2006 Issued
Array ( [id] => 5640534 [patent_doc_number] => 20060278989 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-12-14 [patent_title] => 'Triaxial through-chip connection' [patent_app_type] => utility [patent_app_number] => 11/329887 [patent_app_country] => US [patent_app_date] => 2006-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 123 [patent_figures_cnt] => 123 [patent_no_of_words] => 47580 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0278/20060278989.pdf [firstpage_image] =>[orig_patent_app_number] => 11329887 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/329887
Triaxial through-chip connection Jan 9, 2006 Issued
Array ( [id] => 5217523 [patent_doc_number] => 20070158834 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-07-12 [patent_title] => 'Electrical connections made with dissimilar metals' [patent_app_type] => utility [patent_app_number] => 11/329317 [patent_app_country] => US [patent_app_date] => 2006-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3825 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0158/20070158834.pdf [firstpage_image] =>[orig_patent_app_number] => 11329317 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/329317
Electrical connections made with dissimilar metals Jan 9, 2006 Issued
Array ( [id] => 353023 [patent_doc_number] => 07492048 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-02-17 [patent_title] => 'CMOS sensors having charge pushing regions' [patent_app_type] => utility [patent_app_number] => 11/275497 [patent_app_country] => US [patent_app_date] => 2006-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 21 [patent_no_of_words] => 3344 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/492/07492048.pdf [firstpage_image] =>[orig_patent_app_number] => 11275497 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/275497
CMOS sensors having charge pushing regions Jan 9, 2006 Issued
Menu