Search

Roy Karl Potter

Examiner (ID: 13991, Phone: (571)272-1842 , Office: P/2822 )

Most Active Art Unit
2822
Art Unit(s)
2822, 2508, 2811, 3621
Total Applications
2584
Issued Applications
2409
Pending Applications
46
Abandoned Applications
141

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 817474 [patent_doc_number] => 07411282 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-08-12 [patent_title] => 'LSI package provided with interface module, and transmission line header employed in the package' [patent_app_type] => utility [patent_app_number] => 11/081617 [patent_app_country] => US [patent_app_date] => 2005-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 23 [patent_no_of_words] => 22919 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/411/07411282.pdf [firstpage_image] =>[orig_patent_app_number] => 11081617 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/081617
LSI package provided with interface module, and transmission line header employed in the package Mar 16, 2005 Issued
Array ( [id] => 411977 [patent_doc_number] => 07282781 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-10-16 [patent_title] => 'Semiconductor device with a short-lifetime region and manufacturing method thereof' [patent_app_type] => utility [patent_app_number] => 11/080367 [patent_app_country] => US [patent_app_date] => 2005-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 4273 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/282/07282781.pdf [firstpage_image] =>[orig_patent_app_number] => 11080367 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/080367
Semiconductor device with a short-lifetime region and manufacturing method thereof Mar 14, 2005 Issued
Array ( [id] => 5805177 [patent_doc_number] => 20060091530 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-05-04 [patent_title] => 'Multi-package module with heat spreader' [patent_app_type] => utility [patent_app_number] => 11/076927 [patent_app_country] => US [patent_app_date] => 2005-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1568 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0091/20060091530.pdf [firstpage_image] =>[orig_patent_app_number] => 11076927 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/076927
Multi-package module with heat spreader Mar 10, 2005 Issued
Array ( [id] => 499870 [patent_doc_number] => 07208835 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-04-24 [patent_title] => 'Integrated circuit package and assembly thereof' [patent_app_type] => utility [patent_app_number] => 11/073447 [patent_app_country] => US [patent_app_date] => 2005-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 3425 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/208/07208835.pdf [firstpage_image] =>[orig_patent_app_number] => 11073447 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/073447
Integrated circuit package and assembly thereof Mar 6, 2005 Issued
Array ( [id] => 461371 [patent_doc_number] => 07242091 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-07-10 [patent_title] => 'Stacked semiconductor packages and method therefor' [patent_app_type] => utility [patent_app_number] => 10/906697 [patent_app_country] => US [patent_app_date] => 2005-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 29 [patent_no_of_words] => 5512 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 44 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/242/07242091.pdf [firstpage_image] =>[orig_patent_app_number] => 10906697 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/906697
Stacked semiconductor packages and method therefor Mar 1, 2005 Issued
Array ( [id] => 508586 [patent_doc_number] => 07198983 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-04-03 [patent_title] => 'Solder ball excellent in micro-adhesion preventing properties and wetting properties and method for preventing the micro-adhesion of solder balls' [patent_app_type] => utility [patent_app_number] => 11/067727 [patent_app_country] => US [patent_app_date] => 2005-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 5161 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 41 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/198/07198983.pdf [firstpage_image] =>[orig_patent_app_number] => 11067727 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/067727
Solder ball excellent in micro-adhesion preventing properties and wetting properties and method for preventing the micro-adhesion of solder balls Feb 28, 2005 Issued
Array ( [id] => 7039499 [patent_doc_number] => 20050158918 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-07-21 [patent_title] => 'Masking layer in substrate cavity' [patent_app_type] => utility [patent_app_number] => 11/070547 [patent_app_country] => US [patent_app_date] => 2005-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2300 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0158/20050158918.pdf [firstpage_image] =>[orig_patent_app_number] => 11070547 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/070547
Masking layer in substrate cavity Feb 28, 2005 Issued
Array ( [id] => 526420 [patent_doc_number] => 07187086 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-03-06 [patent_title] => 'Integrated circuit arrangement' [patent_app_type] => utility [patent_app_number] => 11/065148 [patent_app_country] => US [patent_app_date] => 2005-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 14 [patent_no_of_words] => 2996 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/187/07187086.pdf [firstpage_image] =>[orig_patent_app_number] => 11065148 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/065148
Integrated circuit arrangement Feb 24, 2005 Issued
Array ( [id] => 303522 [patent_doc_number] => 07534658 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-05-19 [patent_title] => 'Process for manufacturing microelectronic, microoptoelectronic or micromechanical devices' [patent_app_type] => utility [patent_app_number] => 11/067526 [patent_app_country] => US [patent_app_date] => 2005-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 3714 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/534/07534658.pdf [firstpage_image] =>[orig_patent_app_number] => 11067526 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/067526
Process for manufacturing microelectronic, microoptoelectronic or micromechanical devices Feb 24, 2005 Issued
Array ( [id] => 7019519 [patent_doc_number] => 20050221538 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-10-06 [patent_title] => 'Resin encapsulated semiconductor device and the production method' [patent_app_type] => utility [patent_app_number] => 11/062867 [patent_app_country] => US [patent_app_date] => 2005-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 8434 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0221/20050221538.pdf [firstpage_image] =>[orig_patent_app_number] => 11062867 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/062867
Resin encapsulated semiconductor device and the production method Feb 22, 2005 Issued
Array ( [id] => 408810 [patent_doc_number] => 07285846 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-10-23 [patent_title] => 'Integrated circuit package with ESD protection' [patent_app_type] => utility [patent_app_number] => 11/062527 [patent_app_country] => US [patent_app_date] => 2005-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 13 [patent_no_of_words] => 5628 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/285/07285846.pdf [firstpage_image] =>[orig_patent_app_number] => 11062527 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/062527
Integrated circuit package with ESD protection Feb 21, 2005 Issued
Array ( [id] => 5680939 [patent_doc_number] => 20060197206 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-09-07 [patent_title] => 'Stacked device package for peripheral and center device pad layout device' [patent_app_type] => utility [patent_app_number] => 11/064107 [patent_app_country] => US [patent_app_date] => 2005-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 7396 [patent_no_of_claims] => 54 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0197/20060197206.pdf [firstpage_image] =>[orig_patent_app_number] => 11064107 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/064107
Stacked device package for peripheral and center device pad layout device Feb 21, 2005 Issued
Array ( [id] => 7074845 [patent_doc_number] => 20050148113 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-07-07 [patent_title] => 'Semiconductor multi-package module having inverted second package stacked over die-up flip-chip ball grid array (BGA) package' [patent_app_type] => utility [patent_app_number] => 11/059274 [patent_app_country] => US [patent_app_date] => 2005-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 28439 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0148/20050148113.pdf [firstpage_image] =>[orig_patent_app_number] => 11059274 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/059274
Semiconductor multi-package module having inverted second package stacked over die-up flip-chip ball grid array (BGA) package Feb 15, 2005 Issued
Array ( [id] => 701556 [patent_doc_number] => 07064064 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-06-20 [patent_title] => 'Copper recess process with application to selective capping and electroless plating' [patent_app_type] => utility [patent_app_number] => 11/058783 [patent_app_country] => US [patent_app_date] => 2005-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 2886 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/064/07064064.pdf [firstpage_image] =>[orig_patent_app_number] => 11058783 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/058783
Copper recess process with application to selective capping and electroless plating Feb 15, 2005 Issued
Array ( [id] => 7039592 [patent_doc_number] => 20050158978 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-07-21 [patent_title] => 'Hermetic passivation structure with low capacitance' [patent_app_type] => utility [patent_app_number] => 11/059097 [patent_app_country] => US [patent_app_date] => 2005-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 3285 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0158/20050158978.pdf [firstpage_image] =>[orig_patent_app_number] => 11059097 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/059097
Hermetic passivation structure with low capacitance Feb 14, 2005 Issued
Array ( [id] => 7036894 [patent_doc_number] => 20050156328 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-07-21 [patent_title] => 'Semiconductor device structures including protective layers formed from healable materials' [patent_app_type] => utility [patent_app_number] => 11/053351 [patent_app_country] => US [patent_app_date] => 2005-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6433 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0156/20050156328.pdf [firstpage_image] =>[orig_patent_app_number] => 11053351 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/053351
Semiconductor device structures including protective layers formed from healable materials Feb 7, 2005 Issued
Array ( [id] => 526206 [patent_doc_number] => 07187064 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-03-06 [patent_title] => 'Electrical-interference-isolated transistor structure' [patent_app_type] => utility [patent_app_number] => 11/051677 [patent_app_country] => US [patent_app_date] => 2005-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 1900 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/187/07187064.pdf [firstpage_image] =>[orig_patent_app_number] => 11051677 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/051677
Electrical-interference-isolated transistor structure Feb 6, 2005 Issued
Array ( [id] => 447660 [patent_doc_number] => 07253460 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-08-07 [patent_title] => 'Active matrix panel with two thin film transistors to a pixel' [patent_app_type] => utility [patent_app_number] => 11/049147 [patent_app_country] => US [patent_app_date] => 2005-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 21 [patent_no_of_words] => 6100 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/253/07253460.pdf [firstpage_image] =>[orig_patent_app_number] => 11049147 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/049147
Active matrix panel with two thin film transistors to a pixel Feb 1, 2005 Issued
Array ( [id] => 5664745 [patent_doc_number] => 20060170095 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-08-03 [patent_title] => 'Device package' [patent_app_type] => utility [patent_app_number] => 11/049407 [patent_app_country] => US [patent_app_date] => 2005-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2871 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0170/20060170095.pdf [firstpage_image] =>[orig_patent_app_number] => 11049407 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/049407
Device package Feb 1, 2005 Issued
Array ( [id] => 823595 [patent_doc_number] => 07405145 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-07-29 [patent_title] => 'Ball grid array package substrates with a modified central opening and method for making the same' [patent_app_type] => utility [patent_app_number] => 11/047755 [patent_app_country] => US [patent_app_date] => 2005-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 8202 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/405/07405145.pdf [firstpage_image] =>[orig_patent_app_number] => 11047755 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/047755
Ball grid array package substrates with a modified central opening and method for making the same Feb 1, 2005 Issued
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