
Roy Karl Potter
Examiner (ID: 13991, Phone: (571)272-1842 , Office: P/2822 )
| Most Active Art Unit | 2822 |
| Art Unit(s) | 2822, 2508, 2811, 3621 |
| Total Applications | 2584 |
| Issued Applications | 2409 |
| Pending Applications | 46 |
| Abandoned Applications | 141 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 6768091
[patent_doc_number] => 20030214031
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-11-20
[patent_title] => 'Thermoelectric module package'
[patent_app_type] => new
[patent_app_number] => 10/406237
[patent_app_country] => US
[patent_app_date] => 2003-04-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 23
[patent_figures_cnt] => 23
[patent_no_of_words] => 11228
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 7
[patent_words_short_claim] => 29
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0214/20030214031.pdf
[firstpage_image] =>[orig_patent_app_number] => 10406237
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/406237 | Thermoelectric module package | Apr 3, 2003 | Issued |
Array
(
[id] => 6723477
[patent_doc_number] => 20030205789
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-11-06
[patent_title] => 'Structure and method for securing bussing leads'
[patent_app_type] => new
[patent_app_number] => 10/407648
[patent_app_country] => US
[patent_app_date] => 2003-04-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 3468
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 109
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0205/20030205789.pdf
[firstpage_image] =>[orig_patent_app_number] => 10407648
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/407648 | Structure and method for securing bussing leads | Apr 3, 2003 | Issued |
Array
(
[id] => 560368
[patent_doc_number] => 07161246
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-01-09
[patent_title] => 'Interconnect alloys and methods and apparatus using same'
[patent_app_type] => utility
[patent_app_number] => 10/405796
[patent_app_country] => US
[patent_app_date] => 2003-03-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 12
[patent_no_of_words] => 5758
[patent_no_of_claims] => 78
[patent_no_of_ind_claims] => 17
[patent_words_short_claim] => 13
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/161/07161246.pdf
[firstpage_image] =>[orig_patent_app_number] => 10405796
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/405796 | Interconnect alloys and methods and apparatus using same | Mar 30, 2003 | Issued |
Array
(
[id] => 7610974
[patent_doc_number] => 06841883
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2005-01-11
[patent_title] => 'Multi-dice chip scale semiconductor components and wafer level methods of fabrication'
[patent_app_type] => utility
[patent_app_number] => 10/403937
[patent_app_country] => US
[patent_app_date] => 2003-03-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 27
[patent_figures_cnt] => 62
[patent_no_of_words] => 14675
[patent_no_of_claims] => 71
[patent_no_of_ind_claims] => 21
[patent_words_short_claim] => 64
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/841/06841883.pdf
[firstpage_image] =>[orig_patent_app_number] => 10403937
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/403937 | Multi-dice chip scale semiconductor components and wafer level methods of fabrication | Mar 30, 2003 | Issued |
Array
(
[id] => 1034484
[patent_doc_number] => 06875693
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2005-04-05
[patent_title] => 'Via and metal line interface capable of reducing the incidence of electro-migration induced voids'
[patent_app_type] => utility
[patent_app_number] => 10/400297
[patent_app_country] => US
[patent_app_date] => 2003-03-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 16
[patent_no_of_words] => 5926
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 162
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/875/06875693.pdf
[firstpage_image] =>[orig_patent_app_number] => 10400297
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/400297 | Via and metal line interface capable of reducing the incidence of electro-migration induced voids | Mar 25, 2003 | Issued |
Array
(
[id] => 6727728
[patent_doc_number] => 20030183918
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-10-02
[patent_title] => 'Tape Carrier Package'
[patent_app_type] => new
[patent_app_number] => 10/395232
[patent_app_country] => US
[patent_app_date] => 2003-03-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 3351
[patent_no_of_claims] => 35
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 164
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0183/20030183918.pdf
[firstpage_image] =>[orig_patent_app_number] => 10395232
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/395232 | Tape carrier package | Mar 24, 2003 | Issued |
Array
(
[id] => 1248267
[patent_doc_number] => 06673708
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2004-01-06
[patent_title] => 'Thermal and mechanical attachment of a heatspreader to a flip-chip integrated circuit structure using underfill'
[patent_app_type] => B1
[patent_app_number] => 10/397065
[patent_app_country] => US
[patent_app_date] => 2003-03-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 5
[patent_no_of_words] => 4058
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 46
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/673/06673708.pdf
[firstpage_image] =>[orig_patent_app_number] => 10397065
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/397065 | Thermal and mechanical attachment of a heatspreader to a flip-chip integrated circuit structure using underfill | Mar 24, 2003 | Issued |
Array
(
[id] => 1109029
[patent_doc_number] => 06809404
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-10-26
[patent_title] => 'Semiconductor device'
[patent_app_type] => B2
[patent_app_number] => 10/393917
[patent_app_country] => US
[patent_app_date] => 2003-03-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 10
[patent_no_of_words] => 5006
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 158
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/809/06809404.pdf
[firstpage_image] =>[orig_patent_app_number] => 10393917
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/393917 | Semiconductor device | Mar 23, 2003 | Issued |
Array
(
[id] => 7388524
[patent_doc_number] => 20040017007
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-01-29
[patent_title] => 'Semiconductor package and substrate thereof'
[patent_app_type] => new
[patent_app_number] => 10/394347
[patent_app_country] => US
[patent_app_date] => 2003-03-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 3483
[patent_no_of_claims] => 29
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 66
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0017/20040017007.pdf
[firstpage_image] =>[orig_patent_app_number] => 10394347
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/394347 | Semiconductor package and substrate thereof | Mar 23, 2003 | Issued |
Array
(
[id] => 7421200
[patent_doc_number] => 20040183177
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-09-23
[patent_title] => 'Methods and apparatus for attaching getters to MEMS device housings'
[patent_app_type] => new
[patent_app_number] => 10/393237
[patent_app_country] => US
[patent_app_date] => 2003-03-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 3894
[patent_no_of_claims] => 31
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 50
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0183/20040183177.pdf
[firstpage_image] =>[orig_patent_app_number] => 10393237
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/393237 | Methods and apparatus for attaching getters to MEMS device housings | Mar 19, 2003 | Issued |
Array
(
[id] => 7421424
[patent_doc_number] => 20040183210
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-09-23
[patent_title] => 'Protective layers formed on semiconductor device components so as to reduce or eliminate the occurrence of delamination thereof and cracking therein'
[patent_app_type] => new
[patent_app_number] => 10/391267
[patent_app_country] => US
[patent_app_date] => 2003-03-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 6469
[patent_no_of_claims] => 62
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 46
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0183/20040183210.pdf
[firstpage_image] =>[orig_patent_app_number] => 10391267
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/391267 | Protective layers formed on semiconductor device components so as to reduce or eliminate the occurrence of delamination thereof and cracking therein | Mar 17, 2003 | Issued |
Array
(
[id] => 6794785
[patent_doc_number] => 20030173658
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-09-18
[patent_title] => 'Semiconductor device, manufacturing method for semiconductor device and mounting method for the same'
[patent_app_type] => new
[patent_app_number] => 10/386490
[patent_app_country] => US
[patent_app_date] => 2003-03-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 13
[patent_no_of_words] => 4252
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 51
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0173/20030173658.pdf
[firstpage_image] =>[orig_patent_app_number] => 10386490
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/386490 | Semiconductor device, manufacturing method for semiconductor device and mounting method for the same | Mar 12, 2003 | Issued |
Array
(
[id] => 1155833
[patent_doc_number] => 06764937
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2004-07-20
[patent_title] => 'Solder on a sloped surface'
[patent_app_type] => B1
[patent_app_number] => 10/385487
[patent_app_country] => US
[patent_app_date] => 2003-03-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 14
[patent_no_of_words] => 2954
[patent_no_of_claims] => 26
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 78
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/764/06764937.pdf
[firstpage_image] =>[orig_patent_app_number] => 10385487
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/385487 | Solder on a sloped surface | Mar 11, 2003 | Issued |
Array
(
[id] => 6738272
[patent_doc_number] => 20030155640
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-08-21
[patent_title] => 'Integrated circuit package'
[patent_app_type] => new
[patent_app_number] => 10/387046
[patent_app_country] => US
[patent_app_date] => 2003-03-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 4741
[patent_no_of_claims] => 41
[patent_no_of_ind_claims] => 7
[patent_words_short_claim] => 30
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0155/20030155640.pdf
[firstpage_image] =>[orig_patent_app_number] => 10387046
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/387046 | Integrated circuit package | Mar 11, 2003 | Issued |
Array
(
[id] => 1210965
[patent_doc_number] => 06713861
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-03-30
[patent_title] => 'Method of removing free halogen from a halogenated polymer insulating layer of a semiconductor device and resulting semiconductor device'
[patent_app_type] => B2
[patent_app_number] => 10/382835
[patent_app_country] => US
[patent_app_date] => 2003-03-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 11
[patent_no_of_words] => 3486
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 34
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/713/06713861.pdf
[firstpage_image] =>[orig_patent_app_number] => 10382835
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/382835 | Method of removing free halogen from a halogenated polymer insulating layer of a semiconductor device and resulting semiconductor device | Mar 6, 2003 | Issued |
Array
(
[id] => 6823831
[patent_doc_number] => 20030234453
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-12-25
[patent_title] => 'FLIP CHIP INTERCONNCETION STRUCTURE AND PROCESS OF MAKING THE SAME'
[patent_app_type] => new
[patent_app_number] => 10/248992
[patent_app_country] => US
[patent_app_date] => 2003-03-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 3050
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 106
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0234/20030234453.pdf
[firstpage_image] =>[orig_patent_app_number] => 10248992
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/248992 | Flip chip interconnection structure and process of making the same | Mar 6, 2003 | Issued |
Array
(
[id] => 7610987
[patent_doc_number] => 06841870
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-01-11
[patent_title] => 'Semiconductor device'
[patent_app_type] => utility
[patent_app_number] => 10/382497
[patent_app_country] => US
[patent_app_date] => 2003-03-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 21
[patent_no_of_words] => 6147
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 108
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/841/06841870.pdf
[firstpage_image] =>[orig_patent_app_number] => 10382497
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/382497 | Semiconductor device | Mar 6, 2003 | Issued |
Array
(
[id] => 1134092
[patent_doc_number] => 06784040
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-08-31
[patent_title] => 'Nonvolatile semiconductor memory device and method for fabricating the same'
[patent_app_type] => B2
[patent_app_number] => 10/382508
[patent_app_country] => US
[patent_app_date] => 2003-03-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 52
[patent_figures_cnt] => 172
[patent_no_of_words] => 41853
[patent_no_of_claims] => 59
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 281
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/784/06784040.pdf
[firstpage_image] =>[orig_patent_app_number] => 10382508
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/382508 | Nonvolatile semiconductor memory device and method for fabricating the same | Mar 6, 2003 | Issued |
Array
(
[id] => 6699467
[patent_doc_number] => 20030222347
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-12-04
[patent_title] => 'High aspect ratio fill method and resulting structure'
[patent_app_type] => new
[patent_app_number] => 10/376280
[patent_app_country] => US
[patent_app_date] => 2003-03-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 3431
[patent_no_of_claims] => 65
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 53
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0222/20030222347.pdf
[firstpage_image] =>[orig_patent_app_number] => 10376280
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/376280 | High aspect ratio fill method and resulting structure | Mar 2, 2003 | Issued |
Array
(
[id] => 6662194
[patent_doc_number] => 20030201520
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-10-30
[patent_title] => 'Structure and method of forming a multiple leadframe semiconductor device'
[patent_app_type] => new
[patent_app_number] => 10/374630
[patent_app_country] => US
[patent_app_date] => 2003-02-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 3895
[patent_no_of_claims] => 38
[patent_no_of_ind_claims] => 10
[patent_words_short_claim] => 31
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0201/20030201520.pdf
[firstpage_image] =>[orig_patent_app_number] => 10374630
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/374630 | Structure and method of forming a multiple leadframe semiconductor device | Feb 26, 2003 | Issued |