
Roy Karl Potter
Examiner (ID: 13991, Phone: (571)272-1842 , Office: P/2822 )
| Most Active Art Unit | 2822 |
| Art Unit(s) | 2822, 2508, 2811, 3621 |
| Total Applications | 2584 |
| Issued Applications | 2409 |
| Pending Applications | 46 |
| Abandoned Applications | 141 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 7616707
[patent_doc_number] => 06946735
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-09-20
[patent_title] => 'Side-wall barrier structure and method of fabrication'
[patent_app_type] => utility
[patent_app_number] => 10/307257
[patent_app_country] => US
[patent_app_date] => 2002-11-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 15
[patent_no_of_words] => 2537
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 72
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/946/06946735.pdf
[firstpage_image] =>[orig_patent_app_number] => 10307257
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/307257 | Side-wall barrier structure and method of fabrication | Nov 28, 2002 | Issued |
Array
(
[id] => 6764103
[patent_doc_number] => 20030098501
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-05-29
[patent_title] => 'Semiconductor with a stress reduction layer and manufacturing method therefor'
[patent_app_type] => new
[patent_app_number] => 10/304697
[patent_app_country] => US
[patent_app_date] => 2002-11-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 1218
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 75
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0098/20030098501.pdf
[firstpage_image] =>[orig_patent_app_number] => 10304697
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/304697 | Semiconductor with a stress reduction layer and manufacturing method therefor | Nov 26, 2002 | Issued |
Array
(
[id] => 6768098
[patent_doc_number] => 20030214038
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-11-20
[patent_title] => 'SEMICONDUCTOR DEVICE'
[patent_app_type] => new
[patent_app_number] => 10/303737
[patent_app_country] => US
[patent_app_date] => 2002-11-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 5490
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 146
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0214/20030214038.pdf
[firstpage_image] =>[orig_patent_app_number] => 10303737
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/303737 | Semiconductor device | Nov 25, 2002 | Issued |
Array
(
[id] => 1132587
[patent_doc_number] => 06787904
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-09-07
[patent_title] => 'Semiconductor integrated circuit device'
[patent_app_type] => B2
[patent_app_number] => 10/301837
[patent_app_country] => US
[patent_app_date] => 2002-11-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 20
[patent_no_of_words] => 8645
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 67
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/787/06787904.pdf
[firstpage_image] =>[orig_patent_app_number] => 10301837
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/301837 | Semiconductor integrated circuit device | Nov 21, 2002 | Issued |
Array
(
[id] => 6666734
[patent_doc_number] => 20030111717
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-06-19
[patent_title] => 'Semiconductor device and method of manufacturing the same'
[patent_app_type] => new
[patent_app_number] => 10/299768
[patent_app_country] => US
[patent_app_date] => 2002-11-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 62
[patent_figures_cnt] => 62
[patent_no_of_words] => 11807
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 124
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0111/20030111717.pdf
[firstpage_image] =>[orig_patent_app_number] => 10299768
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/299768 | Semiconductor device and method of manufacturing the same | Nov 19, 2002 | Issued |
Array
(
[id] => 6768110
[patent_doc_number] => 20030214050
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-11-20
[patent_title] => 'SEMICONDUCTOR DEVICE'
[patent_app_type] => new
[patent_app_number] => 10/298927
[patent_app_country] => US
[patent_app_date] => 2002-11-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 3938
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 68
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0214/20030214050.pdf
[firstpage_image] =>[orig_patent_app_number] => 10298927
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/298927 | Semiconductor device | Nov 18, 2002 | Issued |
Array
(
[id] => 1228162
[patent_doc_number] => 06696316
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-02-24
[patent_title] => 'Integrated circuit (IC) package with a microcontroller having an n-bit bus and up to n-pins coupled to the microcontroller'
[patent_app_type] => B2
[patent_app_number] => 10/298504
[patent_app_country] => US
[patent_app_date] => 2002-11-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 1
[patent_no_of_words] => 1831
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 135
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/696/06696316.pdf
[firstpage_image] =>[orig_patent_app_number] => 10298504
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/298504 | Integrated circuit (IC) package with a microcontroller having an n-bit bus and up to n-pins coupled to the microcontroller | Nov 17, 2002 | Issued |
Array
(
[id] => 7632699
[patent_doc_number] => 06664635
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2003-12-16
[patent_title] => 'Lossless microstrip line in CMOS process'
[patent_app_type] => B2
[patent_app_number] => 10/292774
[patent_app_country] => US
[patent_app_date] => 2002-11-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 2202
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 9
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/664/06664635.pdf
[firstpage_image] =>[orig_patent_app_number] => 10292774
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/292774 | Lossless microstrip line in CMOS process | Nov 11, 2002 | Issued |
Array
(
[id] => 1207185
[patent_doc_number] => 06717265
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2004-04-06
[patent_title] => 'Treatment of low-k dielectric material for CMP'
[patent_app_type] => B1
[patent_app_number] => 10/291027
[patent_app_country] => US
[patent_app_date] => 2002-11-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 6
[patent_no_of_words] => 5631
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 60
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/717/06717265.pdf
[firstpage_image] =>[orig_patent_app_number] => 10291027
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/291027 | Treatment of low-k dielectric material for CMP | Nov 7, 2002 | Issued |
Array
(
[id] => 1089156
[patent_doc_number] => 06828217
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-12-07
[patent_title] => 'Dicing process for GAAS/INP and other semiconductor materials'
[patent_app_type] => B2
[patent_app_number] => 10/284707
[patent_app_country] => US
[patent_app_date] => 2002-10-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 17
[patent_no_of_words] => 4478
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 78
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/828/06828217.pdf
[firstpage_image] =>[orig_patent_app_number] => 10284707
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/284707 | Dicing process for GAAS/INP and other semiconductor materials | Oct 30, 2002 | Issued |
Array
(
[id] => 1257348
[patent_doc_number] => 06667543
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-12-23
[patent_title] => 'Optical sensor package'
[patent_app_type] => B1
[patent_app_number] => 10/282537
[patent_app_country] => US
[patent_app_date] => 2002-10-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 8
[patent_no_of_words] => 3707
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 147
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/667/06667543.pdf
[firstpage_image] =>[orig_patent_app_number] => 10282537
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/282537 | Optical sensor package | Oct 28, 2002 | Issued |
Array
(
[id] => 985823
[patent_doc_number] => 06924556
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-08-02
[patent_title] => 'Stack package and manufacturing method thereof'
[patent_app_type] => utility
[patent_app_number] => 10/279977
[patent_app_country] => US
[patent_app_date] => 2002-10-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 28
[patent_no_of_words] => 5273
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 199
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/924/06924556.pdf
[firstpage_image] =>[orig_patent_app_number] => 10279977
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/279977 | Stack package and manufacturing method thereof | Oct 24, 2002 | Issued |
Array
(
[id] => 7627868
[patent_doc_number] => 06806570
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2004-10-19
[patent_title] => 'Thermal compliant semiconductor chip wiring structure for chip scale packaging'
[patent_app_type] => B1
[patent_app_number] => 10/279267
[patent_app_country] => US
[patent_app_date] => 2002-10-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 8
[patent_no_of_words] => 2227
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 9
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/806/06806570.pdf
[firstpage_image] =>[orig_patent_app_number] => 10279267
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/279267 | Thermal compliant semiconductor chip wiring structure for chip scale packaging | Oct 23, 2002 | Issued |
Array
(
[id] => 7625079
[patent_doc_number] => 06724091
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2004-04-20
[patent_title] => 'Flip-chip system and method of making same'
[patent_app_type] => B1
[patent_app_number] => 10/279477
[patent_app_country] => US
[patent_app_date] => 2002-10-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 10
[patent_no_of_words] => 5546
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 5
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/724/06724091.pdf
[firstpage_image] =>[orig_patent_app_number] => 10279477
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/279477 | Flip-chip system and method of making same | Oct 23, 2002 | Issued |
Array
(
[id] => 1170050
[patent_doc_number] => 06756690
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-06-29
[patent_title] => 'Molding die set and semiconductor device fabricated using the same'
[patent_app_type] => B2
[patent_app_number] => 10/277057
[patent_app_country] => US
[patent_app_date] => 2002-10-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 13
[patent_no_of_words] => 5526
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 140
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/756/06756690.pdf
[firstpage_image] =>[orig_patent_app_number] => 10277057
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/277057 | Molding die set and semiconductor device fabricated using the same | Oct 21, 2002 | Issued |
Array
(
[id] => 1086549
[patent_doc_number] => 06831362
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-12-14
[patent_title] => 'Diffusion barrier layer for semiconductor device and fabrication method thereof'
[patent_app_type] => B2
[patent_app_number] => 10/270351
[patent_app_country] => US
[patent_app_date] => 2002-10-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 9
[patent_no_of_words] => 2767
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 26
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/831/06831362.pdf
[firstpage_image] =>[orig_patent_app_number] => 10270351
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/270351 | Diffusion barrier layer for semiconductor device and fabrication method thereof | Oct 14, 2002 | Issued |
Array
(
[id] => 6690950
[patent_doc_number] => 20030038382
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-02-27
[patent_title] => 'Molded plastic package with heat sink and enhanced electrical performance'
[patent_app_type] => new
[patent_app_number] => 10/269332
[patent_app_country] => US
[patent_app_date] => 2002-10-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 3253
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 118
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0038/20030038382.pdf
[firstpage_image] =>[orig_patent_app_number] => 10269332
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/269332 | Molded plastic package with heat sink and enhanced electrical performance | Oct 10, 2002 | Issued |
Array
(
[id] => 6811787
[patent_doc_number] => 20030071337
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-04-17
[patent_title] => 'Laminate film packaged storage device and fabricating method thereof'
[patent_app_type] => new
[patent_app_number] => 10/265797
[patent_app_country] => US
[patent_app_date] => 2002-10-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 3837
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 199
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0071/20030071337.pdf
[firstpage_image] =>[orig_patent_app_number] => 10265797
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/265797 | Laminate film packaged storage device and fabricating method thereof | Oct 6, 2002 | Issued |
Array
(
[id] => 7278837
[patent_doc_number] => 20040061214
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-04-01
[patent_title] => 'Packaged RF power transistor having RF bypassing/output matching network'
[patent_app_type] => new
[patent_app_number] => 10/262217
[patent_app_country] => US
[patent_app_date] => 2002-09-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 2156
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 79
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0061/20040061214.pdf
[firstpage_image] =>[orig_patent_app_number] => 10262217
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/262217 | Packaged RF power transistor having RF bypassing/output matching network | Sep 29, 2002 | Issued |
Array
(
[id] => 1028444
[patent_doc_number] => 06882038
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-04-19
[patent_title] => 'Plating tail design for IC packages'
[patent_app_type] => utility
[patent_app_number] => 10/253677
[patent_app_country] => US
[patent_app_date] => 2002-09-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 3
[patent_no_of_words] => 1534
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 116
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/882/06882038.pdf
[firstpage_image] =>[orig_patent_app_number] => 10253677
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/253677 | Plating tail design for IC packages | Sep 23, 2002 | Issued |