
Roy Karl Potter
Examiner (ID: 13991, Phone: (571)272-1842 , Office: P/2822 )
| Most Active Art Unit | 2822 |
| Art Unit(s) | 2822, 2508, 2811, 3621 |
| Total Applications | 2584 |
| Issued Applications | 2409 |
| Pending Applications | 46 |
| Abandoned Applications | 141 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 1231636
[patent_doc_number] => 06688584
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-02-10
[patent_title] => 'Compound structure for reduced contact resistance'
[patent_app_type] => B2
[patent_app_number] => 09/858617
[patent_app_country] => US
[patent_app_date] => 2001-05-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 11
[patent_no_of_words] => 8597
[patent_no_of_claims] => 88
[patent_no_of_ind_claims] => 37
[patent_words_short_claim] => 36
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/688/06688584.pdf
[firstpage_image] =>[orig_patent_app_number] => 09858617
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/858617 | Compound structure for reduced contact resistance | May 15, 2001 | Issued |
Array
(
[id] => 6880266
[patent_doc_number] => 20010031553
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2001-10-18
[patent_title] => 'Leads under chip in conventional IC package'
[patent_app_type] => new
[patent_app_number] => 09/852868
[patent_app_country] => US
[patent_app_date] => 2001-05-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
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[patent_no_of_words] => 4514
[patent_no_of_claims] => 31
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[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0031/20010031553.pdf
[firstpage_image] =>[orig_patent_app_number] => 09852868
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/852868 | Leads under chip in conventional IC package | May 9, 2001 | Issued |
Array
(
[id] => 6044416
[patent_doc_number] => 20020167071
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-11-14
[patent_title] => 'Guard ring for protecting integrated circuits'
[patent_app_type] => new
[patent_app_number] => 09/851577
[patent_app_country] => US
[patent_app_date] => 2001-05-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
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[patent_no_of_words] => 2480
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[pdf_file] => publications/A1/0167/20020167071.pdf
[firstpage_image] =>[orig_patent_app_number] => 09851577
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/851577 | Guard ring for protecting integrated circuits | May 9, 2001 | Abandoned |
Array
(
[id] => 1120924
[patent_doc_number] => 06798059
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2004-09-28
[patent_title] => 'Multilayer electronic part, its manufacturing method, two-dimensionally arrayed element packaging structure, and its manufacturing method'
[patent_app_type] => B1
[patent_app_number] => 09/830127
[patent_app_country] => US
[patent_app_date] => 2001-04-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 16
[patent_no_of_words] => 6170
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/798/06798059.pdf
[firstpage_image] =>[orig_patent_app_number] => 09830127
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/830127 | Multilayer electronic part, its manufacturing method, two-dimensionally arrayed element packaging structure, and its manufacturing method | Apr 23, 2001 | Issued |
Array
(
[id] => 5997154
[patent_doc_number] => 20020027266
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-03-07
[patent_title] => 'Semiconductor device and a method of manufacturing the same'
[patent_app_type] => new
[patent_app_number] => 09/811467
[patent_app_country] => US
[patent_app_date] => 2001-03-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 26
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[patent_no_of_words] => 12559
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[pdf_file] => publications/A1/0027/20020027266.pdf
[firstpage_image] =>[orig_patent_app_number] => 09811467
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/811467 | Semiconductor device and a method of manufacturing the same | Mar 19, 2001 | Issued |
Array
(
[id] => 1459933
[patent_doc_number] => 06426550
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2002-07-30
[patent_title] => 'Interleaved signal trace routing'
[patent_app_type] => B2
[patent_app_number] => 09/805862
[patent_app_country] => US
[patent_app_date] => 2001-03-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
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[pdf_file] => patents/06/426/06426550.pdf
[firstpage_image] =>[orig_patent_app_number] => 09805862
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/805862 | Interleaved signal trace routing | Mar 13, 2001 | Issued |
Array
(
[id] => 5885896
[patent_doc_number] => 20020011677
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-01-31
[patent_title] => 'Semiconductor device and method of making the same'
[patent_app_type] => new
[patent_app_number] => 09/803947
[patent_app_country] => US
[patent_app_date] => 2001-03-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
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[patent_no_of_words] => 5417
[patent_no_of_claims] => 16
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0011/20020011677.pdf
[firstpage_image] =>[orig_patent_app_number] => 09803947
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/803947 | Semiconductor device with pointed bumps | Mar 12, 2001 | Issued |
Array
(
[id] => 1416223
[patent_doc_number] => 06518161
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-02-11
[patent_title] => 'Method for manufacturing a dual chip in package with a flip chip die mounted on a wire bonded die'
[patent_app_type] => B1
[patent_app_number] => 09/801007
[patent_app_country] => US
[patent_app_date] => 2001-03-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
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[patent_no_of_words] => 1725
[patent_no_of_claims] => 21
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/518/06518161.pdf
[firstpage_image] =>[orig_patent_app_number] => 09801007
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/801007 | Method for manufacturing a dual chip in package with a flip chip die mounted on a wire bonded die | Mar 6, 2001 | Issued |
Array
(
[id] => 1254450
[patent_doc_number] => 06670720
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2003-12-30
[patent_title] => 'Semiconductor chip package with alignment structure'
[patent_app_type] => B2
[patent_app_number] => 09/799179
[patent_app_country] => US
[patent_app_date] => 2001-03-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
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[pdf_file] => patents/06/670/06670720.pdf
[firstpage_image] =>[orig_patent_app_number] => 09799179
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/799179 | Semiconductor chip package with alignment structure | Mar 4, 2001 | Issued |
Array
(
[id] => 6946699
[patent_doc_number] => 20010020549
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2001-09-13
[patent_title] => 'Wiring board, semiconductor device and production methods thereof'
[patent_app_type] => new
[patent_app_number] => 09/797887
[patent_app_country] => US
[patent_app_date] => 2001-03-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
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[patent_no_of_words] => 5968
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[pdf_file] => publications/A1/0020/20010020549.pdf
[firstpage_image] =>[orig_patent_app_number] => 09797887
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/797887 | Wiring board and semiconductor device | Mar 1, 2001 | Issued |
Array
(
[id] => 5918090
[patent_doc_number] => 20020113310
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-08-22
[patent_title] => 'CONDUCTING LINE OF SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF USING ALUMINUM OXIDE LAYER AS HARD MASK'
[patent_app_type] => new
[patent_app_number] => 09/794617
[patent_app_country] => US
[patent_app_date] => 2001-02-28
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[patent_drawing_sheets_cnt] => 6
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[pdf_file] => publications/A1/0113/20020113310.pdf
[firstpage_image] =>[orig_patent_app_number] => 09794617
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/794617 | Conducting line of semiconductor device and manufacturing method thereof using aluminum oxide layer as hard mask | Feb 27, 2001 | Issued |
Array
(
[id] => 1404153
[patent_doc_number] => 06541855
[patent_country] => US
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[patent_issue_date] => 2003-04-01
[patent_title] => 'Printed board unit'
[patent_app_type] => B2
[patent_app_number] => 09/790697
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[firstpage_image] =>[orig_patent_app_number] => 09790697
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/790697 | Printed board unit | Feb 22, 2001 | Issued |
Array
(
[id] => 6891224
[patent_doc_number] => 20010017386
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[patent_title] => 'Memory configuration and method for reading a state from and storing a state in a ferroelectric transistor'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/783187 | Memory configuration and method for reading a state from and storing a state in a ferroelectric transistor | Feb 13, 2001 | Issued |
Array
(
[id] => 6883959
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[patent_title] => 'Semiconductor integrated circuit device and the method of producing the same'
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Array
(
[id] => 1476378
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[patent_title] => 'Multi-chip module'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/774227 | Multi-chip module | Jan 29, 2001 | Issued |
Array
(
[id] => 5982094
[patent_doc_number] => 20020096780
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[patent_title] => 'STRUCTURE OF STACKED INTEGRATED CIRCUITS AND METHOD FOR MANUFACTURING THE SAME'
[patent_app_type] => new
[patent_app_number] => 09/768987
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/768987 | Structure of stacked integrated circuits | Jan 22, 2001 | Issued |
Array
(
[id] => 1554680
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[patent_title] => 'Multi row leadless leadframe package'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/766037 | Multi row leadless leadframe package | Jan 17, 2001 | Issued |
Array
(
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/760777 | Semiconductor device and process for producing the same | Jan 16, 2001 | Issued |
Array
(
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[patent_title] => 'Contact terminal element, contact terminal device'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/759357 | Contact terminal element, contact terminal device | Jan 15, 2001 | Issued |
Array
(
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[patent_title] => 'Wafer level package incorporating dual stress buffer layers for I/O redistribution and method for fabrication'
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[pdf_file] => patents/06/433/06433427.pdf
[firstpage_image] =>[orig_patent_app_number] => 09761487
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/761487 | Wafer level package incorporating dual stress buffer layers for I/O redistribution and method for fabrication | Jan 15, 2001 | Issued |