
Roy Karl Potter
Examiner (ID: 13991, Phone: (571)272-1842 , Office: P/2822 )
| Most Active Art Unit | 2822 |
| Art Unit(s) | 2822, 2508, 2811, 3621 |
| Total Applications | 2584 |
| Issued Applications | 2409 |
| Pending Applications | 46 |
| Abandoned Applications | 141 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 6123505
[patent_doc_number] => 20020074627
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-06-20
[patent_title] => 'Molded plastic package with heat sink and enhanced electrical performance'
[patent_app_type] => new
[patent_app_number] => 09/757729
[patent_app_country] => US
[patent_app_date] => 2001-01-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 3632
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 136
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0074/20020074627.pdf
[firstpage_image] =>[orig_patent_app_number] => 09757729
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/757729 | Molded plastic package with heat sink and enhanced electrical performance | Jan 8, 2001 | Issued |
Array
(
[id] => 6512784
[patent_doc_number] => 20020191835
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-12-19
[patent_title] => 'CAPACITIVE ALIGNMENT STRUCTURE AND METHOD FOR CHIP STACKING'
[patent_app_type] => new
[patent_app_number] => 09/738167
[patent_app_country] => US
[patent_app_date] => 2000-12-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 5149
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 8
[patent_words_short_claim] => 83
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0191/20020191835.pdf
[firstpage_image] =>[orig_patent_app_number] => 09738167
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/738167 | Capacitive alignment structure and method for chip stacking | Dec 14, 2000 | Issued |
Array
(
[id] => 1387126
[patent_doc_number] => 06555906
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2003-04-29
[patent_title] => 'Microelectronic package having a bumpless laminated interconnection layer'
[patent_app_type] => B2
[patent_app_number] => 09/738117
[patent_app_country] => US
[patent_app_date] => 2000-12-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 37
[patent_no_of_words] => 5057
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 3
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[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/555/06555906.pdf
[firstpage_image] =>[orig_patent_app_number] => 09738117
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/738117 | Microelectronic package having a bumpless laminated interconnection layer | Dec 14, 2000 | Issued |
Array
(
[id] => 6123568
[patent_doc_number] => 20020074649
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-06-20
[patent_title] => 'Electronic assembly with high capacity thermal interface and methods of manufacture'
[patent_app_type] => new
[patent_app_number] => 09/737117
[patent_app_country] => US
[patent_app_date] => 2000-12-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 6280
[patent_no_of_claims] => 30
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[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0074/20020074649.pdf
[firstpage_image] =>[orig_patent_app_number] => 09737117
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/737117 | Electronic assembly with high capacity thermal interface | Dec 13, 2000 | Issued |
Array
(
[id] => 6902015
[patent_doc_number] => 20010000924
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2001-05-10
[patent_title] => 'Molded plastic package with heat sink and enhanced electrical performance'
[patent_app_type] => new-utility
[patent_app_number] => 09/737993
[patent_app_country] => US
[patent_app_date] => 2000-12-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 3355
[patent_no_of_claims] => 16
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0000/20010000924.pdf
[firstpage_image] =>[orig_patent_app_number] => 09737993
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/737993 | Molded plastic package with heat sink and enhanced electrical performance | Dec 13, 2000 | Abandoned |
Array
(
[id] => 1519093
[patent_doc_number] => 06501181
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2002-12-31
[patent_title] => 'Arrangement relating to electronic circuitry'
[patent_app_type] => B2
[patent_app_number] => 09/732027
[patent_app_country] => US
[patent_app_date] => 2000-12-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
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[patent_no_of_words] => 4528
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/501/06501181.pdf
[firstpage_image] =>[orig_patent_app_number] => 09732027
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/732027 | Arrangement relating to electronic circuitry | Dec 7, 2000 | Issued |
Array
(
[id] => 1328344
[patent_doc_number] => 06603205
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2003-08-05
[patent_title] => 'MATERIAL FOR ELECTRONIC COMPONENTS, METHOD OF CONNECTING MATERIAL FOR ELECTRONIC COMPONENTS, BALL GRID ARRAY TYPE ELECTRONIC COMPONENTS AND METHOD OF CONNECTING BALL GRID ARRAY TYPE ELECTRONIC COMPONENTS'
[patent_app_type] => B2
[patent_app_number] => 09/729967
[patent_app_country] => US
[patent_app_date] => 2000-12-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 8599
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 31
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/603/06603205.pdf
[firstpage_image] =>[orig_patent_app_number] => 09729967
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/729967 | MATERIAL FOR ELECTRONIC COMPONENTS, METHOD OF CONNECTING MATERIAL FOR ELECTRONIC COMPONENTS, BALL GRID ARRAY TYPE ELECTRONIC COMPONENTS AND METHOD OF CONNECTING BALL GRID ARRAY TYPE ELECTRONIC COMPONENTS | Dec 5, 2000 | Issued |
Array
(
[id] => 1221819
[patent_doc_number] => 06703707
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2004-03-09
[patent_title] => 'Semiconductor device having radiation structure'
[patent_app_type] => B1
[patent_app_number] => 09/717227
[patent_app_country] => US
[patent_app_date] => 2000-11-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 26
[patent_figures_cnt] => 58
[patent_no_of_words] => 24831
[patent_no_of_claims] => 57
[patent_no_of_ind_claims] => 8
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/703/06703707.pdf
[firstpage_image] =>[orig_patent_app_number] => 09717227
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/717227 | Semiconductor device having radiation structure | Nov 21, 2000 | Issued |
Array
(
[id] => 1266582
[patent_doc_number] => 06661096
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-12-09
[patent_title] => 'Wiring material semiconductor device provided with a wiring using the wiring material and method of manufacturing thereof'
[patent_app_type] => B1
[patent_app_number] => 09/604997
[patent_app_country] => US
[patent_app_date] => 2000-11-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 23
[patent_figures_cnt] => 75
[patent_no_of_words] => 14794
[patent_no_of_claims] => 58
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/661/06661096.pdf
[firstpage_image] =>[orig_patent_app_number] => 09604997
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/604997 | Wiring material semiconductor device provided with a wiring using the wiring material and method of manufacturing thereof | Nov 20, 2000 | Issued |
Array
(
[id] => 1428556
[patent_doc_number] => 06504257
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-01-07
[patent_title] => 'Apparatus and method for providing mechanically pre-formed conductive leads'
[patent_app_type] => B1
[patent_app_number] => 09/718597
[patent_app_country] => US
[patent_app_date] => 2000-11-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
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[patent_no_of_words] => 3458
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/504/06504257.pdf
[firstpage_image] =>[orig_patent_app_number] => 09718597
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/718597 | Apparatus and method for providing mechanically pre-formed conductive leads | Nov 20, 2000 | Issued |
Array
(
[id] => 1537186
[patent_doc_number] => 06337510
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-01-08
[patent_title] => 'Stackable QFN semiconductor package'
[patent_app_type] => B1
[patent_app_number] => 09/714157
[patent_app_country] => US
[patent_app_date] => 2000-11-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
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[patent_no_of_words] => 2098
[patent_no_of_claims] => 4
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[pdf_file] => patents/06/337/06337510.pdf
[firstpage_image] =>[orig_patent_app_number] => 09714157
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/714157 | Stackable QFN semiconductor package | Nov 16, 2000 | Issued |
Array
(
[id] => 1407532
[patent_doc_number] => 06538336
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-03-25
[patent_title] => 'Wirebond assembly for high-speed integrated circuits'
[patent_app_type] => B1
[patent_app_number] => 09/715357
[patent_app_country] => US
[patent_app_date] => 2000-11-14
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[pdf_file] => patents/06/538/06538336.pdf
[firstpage_image] =>[orig_patent_app_number] => 09715357
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/715357 | Wirebond assembly for high-speed integrated circuits | Nov 13, 2000 | Issued |
Array
(
[id] => 1471700
[patent_doc_number] => 06407454
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-06-18
[patent_title] => 'Inter-metal dielectric layer'
[patent_app_type] => B1
[patent_app_number] => 09/712727
[patent_app_country] => US
[patent_app_date] => 2000-11-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
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[pdf_file] => patents/06/407/06407454.pdf
[firstpage_image] =>[orig_patent_app_number] => 09712727
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/712727 | Inter-metal dielectric layer | Nov 13, 2000 | Issued |
Array
(
[id] => 1553030
[patent_doc_number] => 06400013
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-06-04
[patent_title] => 'Thermoelectric module with interarray bridges'
[patent_app_type] => B1
[patent_app_number] => 09/709577
[patent_app_country] => US
[patent_app_date] => 2000-11-13
[patent_effective_date] => 0000-00-00
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/400/06400013.pdf
[firstpage_image] =>[orig_patent_app_number] => 09709577
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/709577 | Thermoelectric module with interarray bridges | Nov 12, 2000 | Issued |
Array
(
[id] => 1553066
[patent_doc_number] => 06400019
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-06-04
[patent_title] => 'Semiconductor device with wiring substrate'
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[patent_app_number] => 09/708597
[patent_app_country] => US
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[pdf_file] => patents/06/400/06400019.pdf
[firstpage_image] =>[orig_patent_app_number] => 09708597
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/708597 | Semiconductor device with wiring substrate | Nov 8, 2000 | Issued |
Array
(
[id] => 1597947
[patent_doc_number] => 06492722
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-12-10
[patent_title] => 'Metallized interconnection structure'
[patent_app_type] => B1
[patent_app_number] => 09/707831
[patent_app_country] => US
[patent_app_date] => 2000-11-08
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[pdf_file] => patents/06/492/06492722.pdf
[firstpage_image] =>[orig_patent_app_number] => 09707831
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/707831 | Metallized interconnection structure | Nov 7, 2000 | Issued |
Array
(
[id] => 4386024
[patent_doc_number] => 06304000
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-10-16
[patent_title] => 'Semiconductor device comprising silicone adhesive sheet'
[patent_app_type] => 1
[patent_app_number] => 9/706561
[patent_app_country] => US
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[pdf_file] => patents/06/304/06304000.pdf
[firstpage_image] =>[orig_patent_app_number] => 706561
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/706561 | Semiconductor device comprising silicone adhesive sheet | Nov 5, 2000 | Issued |
Array
(
[id] => 1273920
[patent_doc_number] => 06649490
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-11-18
[patent_title] => 'METHODS FOR FORMING INTEGRATED CIRCUIT DEVICES THROUGH SELECTIVE ETCHING OF AN INSULATION LAYER TO INCREASE THE SELF-ALIGNED CONTACT AREA ADJACENT A SEMICONDUCTOR REGION AND INTEGRATED CIRCUIT DEVICES FORMED THEREBY'
[patent_app_type] => B1
[patent_app_number] => 09/702597
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[pdf_file] => patents/06/649/06649490.pdf
[firstpage_image] =>[orig_patent_app_number] => 09702597
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/702597 | METHODS FOR FORMING INTEGRATED CIRCUIT DEVICES THROUGH SELECTIVE ETCHING OF AN INSULATION LAYER TO INCREASE THE SELF-ALIGNED CONTACT AREA ADJACENT A SEMICONDUCTOR REGION AND INTEGRATED CIRCUIT DEVICES FORMED THEREBY | Oct 30, 2000 | Issued |
Array
(
[id] => 1428502
[patent_doc_number] => 06504250
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-01-07
[patent_title] => 'Integrated circuit device with reduced cross talk'
[patent_app_type] => B1
[patent_app_number] => 09/695598
[patent_app_country] => US
[patent_app_date] => 2000-10-23
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/06/504/06504250.pdf
[firstpage_image] =>[orig_patent_app_number] => 09695598
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/695598 | Integrated circuit device with reduced cross talk | Oct 22, 2000 | Issued |
Array
(
[id] => 1421366
[patent_doc_number] => 06522006
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-02-18
[patent_title] => 'Low dielectric constant material in integrated circuit'
[patent_app_type] => B1
[patent_app_number] => 09/695020
[patent_app_country] => US
[patent_app_date] => 2000-10-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
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[pdf_file] => patents/06/522/06522006.pdf
[firstpage_image] =>[orig_patent_app_number] => 09695020
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/695020 | Low dielectric constant material in integrated circuit | Oct 22, 2000 | Issued |