Search

Roy Karl Potter

Examiner (ID: 13991, Phone: (571)272-1842 , Office: P/2822 )

Most Active Art Unit
2822
Art Unit(s)
2822, 2508, 2811, 3621
Total Applications
2584
Issued Applications
2409
Pending Applications
46
Abandoned Applications
141

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1214388 [patent_doc_number] => 06710457 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-03-23 [patent_title] => 'Integrated circuit carrier' [patent_app_type] => B1 [patent_app_number] => 09/693277 [patent_app_country] => US [patent_app_date] => 2000-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 14 [patent_no_of_words] => 2931 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/710/06710457.pdf [firstpage_image] =>[orig_patent_app_number] => 09693277 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/693277
Integrated circuit carrier Oct 19, 2000 Issued
Array ( [id] => 484463 [patent_doc_number] => 07221043 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-05-22 [patent_title] => 'Integrated circuit carrier with recesses' [patent_app_type] => utility [patent_app_number] => 09/693707 [patent_app_country] => US [patent_app_date] => 2000-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 14 [patent_no_of_words] => 3033 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/221/07221043.pdf [firstpage_image] =>[orig_patent_app_number] => 09693707 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/693707
Integrated circuit carrier with recesses Oct 19, 2000 Issued
Array ( [id] => 7640287 [patent_doc_number] => 06395627 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-28 [patent_title] => 'Semiconductor device a burried wiring structure and process for fabricating the same' [patent_app_type] => B1 [patent_app_number] => 09/691187 [patent_app_country] => US [patent_app_date] => 2000-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 11 [patent_no_of_words] => 4012 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 5 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/395/06395627.pdf [firstpage_image] =>[orig_patent_app_number] => 09691187 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/691187
Semiconductor device a burried wiring structure and process for fabricating the same Oct 18, 2000 Issued
Array ( [id] => 4401055 [patent_doc_number] => 06297517 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-02 [patent_title] => 'Semiconductor device and method of fabricating the same' [patent_app_type] => 1 [patent_app_number] => 9/688197 [patent_app_country] => US [patent_app_date] => 2000-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 48 [patent_no_of_words] => 7330 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/297/06297517.pdf [firstpage_image] =>[orig_patent_app_number] => 688197 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/688197
Semiconductor device and method of fabricating the same Oct 15, 2000 Issued
Array ( [id] => 1288767 [patent_doc_number] => 06639318 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-10-28 [patent_title] => 'Integrated circuit device and its manufacturing method' [patent_app_type] => B1 [patent_app_number] => 09/647917 [patent_app_country] => US [patent_app_date] => 2000-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 3704 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 44 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/639/06639318.pdf [firstpage_image] =>[orig_patent_app_number] => 09647917 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/647917
Integrated circuit device and its manufacturing method Oct 12, 2000 Issued
Array ( [id] => 1306067 [patent_doc_number] => 06621137 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-09-16 [patent_title] => 'MEMS device integrated chip package, and method of making same' [patent_app_type] => B1 [patent_app_number] => 09/687907 [patent_app_country] => US [patent_app_date] => 2000-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 33 [patent_no_of_words] => 7761 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/621/06621137.pdf [firstpage_image] =>[orig_patent_app_number] => 09687907 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/687907
MEMS device integrated chip package, and method of making same Oct 11, 2000 Issued
Array ( [id] => 1293531 [patent_doc_number] => 06630740 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-10-07 [patent_title] => 'Semiconductor device' [patent_app_type] => B1 [patent_app_number] => 09/671737 [patent_app_country] => US [patent_app_date] => 2000-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 11 [patent_no_of_words] => 3762 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/630/06630740.pdf [firstpage_image] =>[orig_patent_app_number] => 09671737 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/671737
Semiconductor device Sep 28, 2000 Issued
Array ( [id] => 1448122 [patent_doc_number] => 06369445 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-09 [patent_title] => 'Method and apparatus for edge connection between elements of an integrated circuit' [patent_app_type] => B1 [patent_app_number] => 09/670107 [patent_app_country] => US [patent_app_date] => 2000-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3112 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/369/06369445.pdf [firstpage_image] =>[orig_patent_app_number] => 09670107 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/670107
Method and apparatus for edge connection between elements of an integrated circuit Sep 25, 2000 Issued
Array ( [id] => 1597962 [patent_doc_number] => 06492726 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-10 [patent_title] => 'Chip scale packaging with multi-layer flip chip arrangement and ball grid array interconnection' [patent_app_type] => B1 [patent_app_number] => 09/667837 [patent_app_country] => US [patent_app_date] => 2000-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 4693 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 396 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/492/06492726.pdf [firstpage_image] =>[orig_patent_app_number] => 09667837 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/667837
Chip scale packaging with multi-layer flip chip arrangement and ball grid array interconnection Sep 21, 2000 Issued
Array ( [id] => 1563173 [patent_doc_number] => 06362529 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-26 [patent_title] => 'Stacked semiconductor device' [patent_app_type] => B1 [patent_app_number] => 09/667587 [patent_app_country] => US [patent_app_date] => 2000-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 2824 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/362/06362529.pdf [firstpage_image] =>[orig_patent_app_number] => 09667587 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/667587
Stacked semiconductor device Sep 21, 2000 Issued
Array ( [id] => 1210960 [patent_doc_number] => 06713859 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-03-30 [patent_title] => 'Direct build-up layer on an encapsulated die package having a moisture barrier structure' [patent_app_type] => B1 [patent_app_number] => 09/660757 [patent_app_country] => US [patent_app_date] => 2000-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 34 [patent_no_of_words] => 3858 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/713/06713859.pdf [firstpage_image] =>[orig_patent_app_number] => 09660757 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/660757
Direct build-up layer on an encapsulated die package having a moisture barrier structure Sep 12, 2000 Issued
Array ( [id] => 1509559 [patent_doc_number] => 06441500 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-27 [patent_title] => 'Semiconductor device having resin members provided separately corresponding to externally connecting electrodes' [patent_app_type] => B1 [patent_app_number] => 09/660477 [patent_app_country] => US [patent_app_date] => 2000-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 31 [patent_no_of_words] => 4997 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/441/06441500.pdf [firstpage_image] =>[orig_patent_app_number] => 09660477 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/660477
Semiconductor device having resin members provided separately corresponding to externally connecting electrodes Sep 11, 2000 Issued
Array ( [id] => 1583023 [patent_doc_number] => 06424027 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-23 [patent_title] => 'Low pass filter integral with semiconductor package' [patent_app_type] => B1 [patent_app_number] => 09/659927 [patent_app_country] => US [patent_app_date] => 2000-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 4197 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/424/06424027.pdf [firstpage_image] =>[orig_patent_app_number] => 09659927 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/659927
Low pass filter integral with semiconductor package Sep 11, 2000 Issued
Array ( [id] => 1391622 [patent_doc_number] => 06552416 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-04-22 [patent_title] => 'Multiple die lead frame package with enhanced die-to-die interconnect routing using internal lead trace wiring' [patent_app_type] => B1 [patent_app_number] => 09/659017 [patent_app_country] => US [patent_app_date] => 2000-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 15 [patent_no_of_words] => 3423 [patent_no_of_claims] => 41 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/552/06552416.pdf [firstpage_image] =>[orig_patent_app_number] => 09659017 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/659017
Multiple die lead frame package with enhanced die-to-die interconnect routing using internal lead trace wiring Sep 7, 2000 Issued
Array ( [id] => 1214385 [patent_doc_number] => 06710456 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-03-23 [patent_title] => 'Composite interposer for BGA packages' [patent_app_type] => B1 [patent_app_number] => 09/652977 [patent_app_country] => US [patent_app_date] => 2000-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 4289 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 39 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/710/06710456.pdf [firstpage_image] =>[orig_patent_app_number] => 09652977 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/652977
Composite interposer for BGA packages Aug 30, 2000 Issued
Array ( [id] => 1384944 [patent_doc_number] => 06559537 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-05-06 [patent_title] => 'Ball grid array packages with thermally conductive containers' [patent_app_type] => B1 [patent_app_number] => 09/653127 [patent_app_country] => US [patent_app_date] => 2000-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 12 [patent_no_of_words] => 2833 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 27 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/559/06559537.pdf [firstpage_image] =>[orig_patent_app_number] => 09653127 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/653127
Ball grid array packages with thermally conductive containers Aug 30, 2000 Issued
Array ( [id] => 1480604 [patent_doc_number] => 06452253 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-17 [patent_title] => 'Method and apparatus for magnetic shielding of an integrated circuit' [patent_app_type] => B1 [patent_app_number] => 09/651997 [patent_app_country] => US [patent_app_date] => 2000-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2455 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 18 [patent_words_short_claim] => 31 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/452/06452253.pdf [firstpage_image] =>[orig_patent_app_number] => 09651997 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/651997
Method and apparatus for magnetic shielding of an integrated circuit Aug 30, 2000 Issued
Array ( [id] => 1396330 [patent_doc_number] => 06548892 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-04-15 [patent_title] => 'Low k dielectric insulator and method of forming semiconductor circuit structures' [patent_app_type] => B1 [patent_app_number] => 09/653297 [patent_app_country] => US [patent_app_date] => 2000-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 19 [patent_no_of_words] => 5537 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 33 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/548/06548892.pdf [firstpage_image] =>[orig_patent_app_number] => 09653297 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/653297
Low k dielectric insulator and method of forming semiconductor circuit structures Aug 30, 2000 Issued
Array ( [id] => 1568437 [patent_doc_number] => 06376899 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-23 [patent_title] => 'Planar guard ring' [patent_app_type] => B1 [patent_app_number] => 09/651367 [patent_app_country] => US [patent_app_date] => 2000-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 2228 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/376/06376899.pdf [firstpage_image] =>[orig_patent_app_number] => 09651367 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/651367
Planar guard ring Aug 28, 2000 Issued
Array ( [id] => 7645247 [patent_doc_number] => 06472725 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-29 [patent_title] => 'Technique for attaching die to leads' [patent_app_type] => B1 [patent_app_number] => 09/645910 [patent_app_country] => US [patent_app_date] => 2000-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 4599 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 6 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/472/06472725.pdf [firstpage_image] =>[orig_patent_app_number] => 09645910 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/645910
Technique for attaching die to leads Aug 24, 2000 Issued
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