
Roy Karl Potter
Examiner (ID: 13991, Phone: (571)272-1842 , Office: P/2822 )
| Most Active Art Unit | 2822 |
| Art Unit(s) | 2822, 2508, 2811, 3621 |
| Total Applications | 2584 |
| Issued Applications | 2409 |
| Pending Applications | 46 |
| Abandoned Applications | 141 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 1214388
[patent_doc_number] => 06710457
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2004-03-23
[patent_title] => 'Integrated circuit carrier'
[patent_app_type] => B1
[patent_app_number] => 09/693277
[patent_app_country] => US
[patent_app_date] => 2000-10-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 14
[patent_no_of_words] => 2931
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/710/06710457.pdf
[firstpage_image] =>[orig_patent_app_number] => 09693277
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/693277 | Integrated circuit carrier | Oct 19, 2000 | Issued |
Array
(
[id] => 484463
[patent_doc_number] => 07221043
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2007-05-22
[patent_title] => 'Integrated circuit carrier with recesses'
[patent_app_type] => utility
[patent_app_number] => 09/693707
[patent_app_country] => US
[patent_app_date] => 2000-10-20
[patent_effective_date] => 0000-00-00
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/221/07221043.pdf
[firstpage_image] =>[orig_patent_app_number] => 09693707
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/693707 | Integrated circuit carrier with recesses | Oct 19, 2000 | Issued |
Array
(
[id] => 7640287
[patent_doc_number] => 06395627
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-05-28
[patent_title] => 'Semiconductor device a burried wiring structure and process for fabricating the same'
[patent_app_type] => B1
[patent_app_number] => 09/691187
[patent_app_country] => US
[patent_app_date] => 2000-10-19
[patent_effective_date] => 0000-00-00
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/691187 | Semiconductor device a burried wiring structure and process for fabricating the same | Oct 18, 2000 | Issued |
Array
(
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[patent_doc_number] => 06297517
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-10-02
[patent_title] => 'Semiconductor device and method of fabricating the same'
[patent_app_type] => 1
[patent_app_number] => 9/688197
[patent_app_country] => US
[patent_app_date] => 2000-10-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/688197 | Semiconductor device and method of fabricating the same | Oct 15, 2000 | Issued |
Array
(
[id] => 1288767
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[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-10-28
[patent_title] => 'Integrated circuit device and its manufacturing method'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/647917 | Integrated circuit device and its manufacturing method | Oct 12, 2000 | Issued |
Array
(
[id] => 1306067
[patent_doc_number] => 06621137
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[patent_kind] => B1
[patent_issue_date] => 2003-09-16
[patent_title] => 'MEMS device integrated chip package, and method of making same'
[patent_app_type] => B1
[patent_app_number] => 09/687907
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[firstpage_image] =>[orig_patent_app_number] => 09687907
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Array
(
[id] => 1293531
[patent_doc_number] => 06630740
[patent_country] => US
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[patent_issue_date] => 2003-10-07
[patent_title] => 'Semiconductor device'
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[patent_app_number] => 09/671737
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[patent_effective_date] => 0000-00-00
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[firstpage_image] =>[orig_patent_app_number] => 09671737
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/671737 | Semiconductor device | Sep 28, 2000 | Issued |
Array
(
[id] => 1448122
[patent_doc_number] => 06369445
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-04-09
[patent_title] => 'Method and apparatus for edge connection between elements of an integrated circuit'
[patent_app_type] => B1
[patent_app_number] => 09/670107
[patent_app_country] => US
[patent_app_date] => 2000-09-26
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[pdf_file] => patents/06/369/06369445.pdf
[firstpage_image] =>[orig_patent_app_number] => 09670107
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/670107 | Method and apparatus for edge connection between elements of an integrated circuit | Sep 25, 2000 | Issued |
Array
(
[id] => 1597962
[patent_doc_number] => 06492726
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-12-10
[patent_title] => 'Chip scale packaging with multi-layer flip chip arrangement and ball grid array interconnection'
[patent_app_type] => B1
[patent_app_number] => 09/667837
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[pdf_file] => patents/06/492/06492726.pdf
[firstpage_image] =>[orig_patent_app_number] => 09667837
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/667837 | Chip scale packaging with multi-layer flip chip arrangement and ball grid array interconnection | Sep 21, 2000 | Issued |
Array
(
[id] => 1563173
[patent_doc_number] => 06362529
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-03-26
[patent_title] => 'Stacked semiconductor device'
[patent_app_type] => B1
[patent_app_number] => 09/667587
[patent_app_country] => US
[patent_app_date] => 2000-09-22
[patent_effective_date] => 0000-00-00
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[firstpage_image] =>[orig_patent_app_number] => 09667587
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/667587 | Stacked semiconductor device | Sep 21, 2000 | Issued |
Array
(
[id] => 1210960
[patent_doc_number] => 06713859
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2004-03-30
[patent_title] => 'Direct build-up layer on an encapsulated die package having a moisture barrier structure'
[patent_app_type] => B1
[patent_app_number] => 09/660757
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[pdf_file] => patents/06/713/06713859.pdf
[firstpage_image] =>[orig_patent_app_number] => 09660757
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/660757 | Direct build-up layer on an encapsulated die package having a moisture barrier structure | Sep 12, 2000 | Issued |
Array
(
[id] => 1509559
[patent_doc_number] => 06441500
[patent_country] => US
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[patent_issue_date] => 2002-08-27
[patent_title] => 'Semiconductor device having resin members provided separately corresponding to externally connecting electrodes'
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Array
(
[id] => 1583023
[patent_doc_number] => 06424027
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-07-23
[patent_title] => 'Low pass filter integral with semiconductor package'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/659927 | Low pass filter integral with semiconductor package | Sep 11, 2000 | Issued |
Array
(
[id] => 1391622
[patent_doc_number] => 06552416
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[patent_kind] => B1
[patent_issue_date] => 2003-04-22
[patent_title] => 'Multiple die lead frame package with enhanced die-to-die interconnect routing using internal lead trace wiring'
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[patent_app_number] => 09/659017
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/659017 | Multiple die lead frame package with enhanced die-to-die interconnect routing using internal lead trace wiring | Sep 7, 2000 | Issued |
Array
(
[id] => 1214385
[patent_doc_number] => 06710456
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[patent_title] => 'Composite interposer for BGA packages'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/652977 | Composite interposer for BGA packages | Aug 30, 2000 | Issued |
Array
(
[id] => 1384944
[patent_doc_number] => 06559537
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[patent_title] => 'Ball grid array packages with thermally conductive containers'
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[patent_app_number] => 09/653127
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/653127 | Ball grid array packages with thermally conductive containers | Aug 30, 2000 | Issued |
Array
(
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[patent_title] => 'Method and apparatus for magnetic shielding of an integrated circuit'
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Array
(
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Array
(
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Array
(
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[firstpage_image] =>[orig_patent_app_number] => 09645910
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/645910 | Technique for attaching die to leads | Aug 24, 2000 | Issued |