
Roy Karl Potter
Examiner (ID: 13991, Phone: (571)272-1842 , Office: P/2822 )
| Most Active Art Unit | 2822 |
| Art Unit(s) | 2822, 2508, 2811, 3621 |
| Total Applications | 2584 |
| Issued Applications | 2409 |
| Pending Applications | 46 |
| Abandoned Applications | 141 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 1352527
[patent_doc_number] => 06583506
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-06-24
[patent_title] => 'Semiconductor device'
[patent_app_type] => B1
[patent_app_number] => 09/622837
[patent_app_country] => US
[patent_app_date] => 2000-08-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 36
[patent_no_of_words] => 7318
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 183
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/583/06583506.pdf
[firstpage_image] =>[orig_patent_app_number] => 09622837
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/622837 | Semiconductor device | Aug 23, 2000 | Issued |
Array
(
[id] => 4331859
[patent_doc_number] => 06329706
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-12-11
[patent_title] => 'Leadframe using chip pad as heat conducting path and semiconductor package adopting the same'
[patent_app_type] => 1
[patent_app_number] => 9/644097
[patent_app_country] => US
[patent_app_date] => 2000-08-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 8
[patent_no_of_words] => 3887
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 133
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/329/06329706.pdf
[firstpage_image] =>[orig_patent_app_number] => 644097
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/644097 | Leadframe using chip pad as heat conducting path and semiconductor package adopting the same | Aug 22, 2000 | Issued |
Array
(
[id] => 1534648
[patent_doc_number] => 06410980
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-06-25
[patent_title] => 'Electronic part with groove in lead'
[patent_app_type] => B1
[patent_app_number] => 09/640777
[patent_app_country] => US
[patent_app_date] => 2000-08-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 19
[patent_no_of_words] => 4786
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 71
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/410/06410980.pdf
[firstpage_image] =>[orig_patent_app_number] => 09640777
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/640777 | Electronic part with groove in lead | Aug 17, 2000 | Issued |
Array
(
[id] => 1486804
[patent_doc_number] => 06365966
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-04-02
[patent_title] => 'Stacked chip scale package'
[patent_app_type] => B1
[patent_app_number] => 09/632677
[patent_app_country] => US
[patent_app_date] => 2000-08-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 9
[patent_no_of_words] => 3742
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 287
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/365/06365966.pdf
[firstpage_image] =>[orig_patent_app_number] => 09632677
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/632677 | Stacked chip scale package | Aug 6, 2000 | Issued |
Array
(
[id] => 1421714
[patent_doc_number] => 06509642
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-01-21
[patent_title] => 'Integrated circuit package'
[patent_app_type] => B1
[patent_app_number] => 09/628067
[patent_app_country] => US
[patent_app_date] => 2000-07-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 5
[patent_no_of_words] => 2042
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 83
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/509/06509642.pdf
[firstpage_image] =>[orig_patent_app_number] => 09628067
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/628067 | Integrated circuit package | Jul 27, 2000 | Issued |
Array
(
[id] => 1603259
[patent_doc_number] => 06433439
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-08-13
[patent_title] => 'Device with security integrated circuit'
[patent_app_type] => B1
[patent_app_number] => 09/486527
[patent_app_country] => US
[patent_app_date] => 2000-07-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 15
[patent_no_of_words] => 3139
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 94
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/433/06433439.pdf
[firstpage_image] =>[orig_patent_app_number] => 09486527
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/486527 | Device with security integrated circuit | Jul 25, 2000 | Issued |
Array
(
[id] => 1502416
[patent_doc_number] => 06486563
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-11-26
[patent_title] => 'Wafer scale packaging scheme'
[patent_app_type] => B1
[patent_app_number] => 09/619017
[patent_app_country] => US
[patent_app_date] => 2000-07-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 17
[patent_no_of_words] => 4262
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 116
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/486/06486563.pdf
[firstpage_image] =>[orig_patent_app_number] => 09619017
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/619017 | Wafer scale packaging scheme | Jul 18, 2000 | Issued |
Array
(
[id] => 1588635
[patent_doc_number] => 06482663
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-11-19
[patent_title] => 'Silicon substrate having a recess for receiving an element, and a method of producing such a recess'
[patent_app_type] => B1
[patent_app_number] => 09/613807
[patent_app_country] => US
[patent_app_date] => 2000-07-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 3
[patent_no_of_words] => 1222
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 87
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/482/06482663.pdf
[firstpage_image] =>[orig_patent_app_number] => 09613807
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/613807 | Silicon substrate having a recess for receiving an element, and a method of producing such a recess | Jul 10, 2000 | Issued |
Array
(
[id] => 7647038
[patent_doc_number] => 06476480
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-11-05
[patent_title] => 'Press-fit IC power package and method therefor'
[patent_app_type] => B1
[patent_app_number] => 09/612729
[patent_app_country] => US
[patent_app_date] => 2000-07-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 10
[patent_no_of_words] => 3203
[patent_no_of_claims] => 55
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[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/476/06476480.pdf
[firstpage_image] =>[orig_patent_app_number] => 09612729
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/612729 | Press-fit IC power package and method therefor | Jul 9, 2000 | Issued |
Array
(
[id] => 4331803
[patent_doc_number] => 06329702
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-12-11
[patent_title] => 'High frequency carrier'
[patent_app_type] => 1
[patent_app_number] => 9/611057
[patent_app_country] => US
[patent_app_date] => 2000-07-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 6
[patent_no_of_words] => 2999
[patent_no_of_claims] => 31
[patent_no_of_ind_claims] => 8
[patent_words_short_claim] => 24
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/329/06329702.pdf
[firstpage_image] =>[orig_patent_app_number] => 611057
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/611057 | High frequency carrier | Jul 5, 2000 | Issued |
Array
(
[id] => 1497169
[patent_doc_number] => 06404054
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-06-11
[patent_title] => 'Tungsten layer formation method for semiconductor device and semiconductor device using the same'
[patent_app_type] => B1
[patent_app_number] => 09/609927
[patent_app_country] => US
[patent_app_date] => 2000-07-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 5
[patent_no_of_words] => 2728
[patent_no_of_claims] => 7
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[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/404/06404054.pdf
[firstpage_image] =>[orig_patent_app_number] => 09609927
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/609927 | Tungsten layer formation method for semiconductor device and semiconductor device using the same | Jul 4, 2000 | Issued |
Array
(
[id] => 1480707
[patent_doc_number] => 06452278
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-09-17
[patent_title] => 'Low profile package for plural semiconductor dies'
[patent_app_type] => B1
[patent_app_number] => 09/608197
[patent_app_country] => US
[patent_app_date] => 2000-06-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
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[patent_no_of_words] => 2281
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/452/06452278.pdf
[firstpage_image] =>[orig_patent_app_number] => 09608197
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/608197 | Low profile package for plural semiconductor dies | Jun 29, 2000 | Issued |
Array
(
[id] => 1476429
[patent_doc_number] => 06388333
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-05-14
[patent_title] => 'Semiconductor device having protruding electrodes higher than a sealed portion'
[patent_app_type] => B1
[patent_app_number] => 09/605687
[patent_app_country] => US
[patent_app_date] => 2000-06-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 30
[patent_figures_cnt] => 59
[patent_no_of_words] => 15504
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 3
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[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/388/06388333.pdf
[firstpage_image] =>[orig_patent_app_number] => 09605687
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/605687 | Semiconductor device having protruding electrodes higher than a sealed portion | Jun 26, 2000 | Issued |
Array
(
[id] => 4259391
[patent_doc_number] => 06258704
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-07-10
[patent_title] => 'Methods for fabricating dimpled contacts for metal-to-semiconductor connections'
[patent_app_type] => 1
[patent_app_number] => 9/596161
[patent_app_country] => US
[patent_app_date] => 2000-06-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
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[patent_no_of_words] => 4790
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[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/258/06258704.pdf
[firstpage_image] =>[orig_patent_app_number] => 596161
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/596161 | Methods for fabricating dimpled contacts for metal-to-semiconductor connections | Jun 15, 2000 | Issued |
Array
(
[id] => 4325459
[patent_doc_number] => 06329295
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-12-11
[patent_title] => 'Semiconductor device capable of having amorphous carbon fluoride film of low dielectric constant as interlayer insulation material and method of manufacturing the same'
[patent_app_type] => 1
[patent_app_number] => 9/594037
[patent_app_country] => US
[patent_app_date] => 2000-06-15
[patent_effective_date] => 0000-00-00
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/329/06329295.pdf
[firstpage_image] =>[orig_patent_app_number] => 594037
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/594037 | Semiconductor device capable of having amorphous carbon fluoride film of low dielectric constant as interlayer insulation material and method of manufacturing the same | Jun 14, 2000 | Issued |
Array
(
[id] => 1300089
[patent_doc_number] => 06627953
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-09-30
[patent_title] => 'High density electronic circuit modules'
[patent_app_type] => B1
[patent_app_number] => 09/592246
[patent_app_country] => US
[patent_app_date] => 2000-06-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 25
[patent_figures_cnt] => 67
[patent_no_of_words] => 10286
[patent_no_of_claims] => 13
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/627/06627953.pdf
[firstpage_image] =>[orig_patent_app_number] => 09592246
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/592246 | High density electronic circuit modules | Jun 12, 2000 | Issued |
Array
(
[id] => 1197825
[patent_doc_number] => 06727579
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2004-04-27
[patent_title] => 'ELECTRICAL CONTACT STRUCTURES FORMED BY CONFIGURING A FLEXIBLE WIRE TO HAVE A SPRINGABLE SHAPE AND OVERCOATING THE WIRE WITH AT LEAST ONE LAYER OF A RESILIENT CONDUCTIVE MATERIAL, METHODS OF MOUNTING THE CONTACT STRUCTURES TO ELECTRONIC COMPONENTS, AND APPLICATIONS FOR EMPLOYING THE CONTACT STRUCTURES'
[patent_app_type] => B1
[patent_app_number] => 09/592487
[patent_app_country] => US
[patent_app_date] => 2000-06-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 60
[patent_figures_cnt] => 175
[patent_no_of_words] => 80016
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/727/06727579.pdf
[firstpage_image] =>[orig_patent_app_number] => 09592487
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/592487 | ELECTRICAL CONTACT STRUCTURES FORMED BY CONFIGURING A FLEXIBLE WIRE TO HAVE A SPRINGABLE SHAPE AND OVERCOATING THE WIRE WITH AT LEAST ONE LAYER OF A RESILIENT CONDUCTIVE MATERIAL, METHODS OF MOUNTING THE CONTACT STRUCTURES TO ELECTRONIC COMPONENTS, AND APPLICATIONS FOR EMPLOYING THE CONTACT STRUCTURES | Jun 7, 2000 | Issued |
Array
(
[id] => 1571221
[patent_doc_number] => 06498394
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-12-24
[patent_title] => 'IC packages with diamond substrate thermal conductor'
[patent_app_type] => B1
[patent_app_number] => 09/569597
[patent_app_country] => US
[patent_app_date] => 2000-05-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
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[pdf_file] => patents/06/498/06498394.pdf
[firstpage_image] =>[orig_patent_app_number] => 09569597
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/569597 | IC packages with diamond substrate thermal conductor | May 8, 2000 | Issued |
Array
(
[id] => 7647028
[patent_doc_number] => 06476490
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-11-05
[patent_title] => 'Contact openings, electrical connections and interconnections for integrated circuitry'
[patent_app_type] => B1
[patent_app_number] => 09/565197
[patent_app_country] => US
[patent_app_date] => 2000-05-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/476/06476490.pdf
[firstpage_image] =>[orig_patent_app_number] => 09565197
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/565197 | Contact openings, electrical connections and interconnections for integrated circuitry | May 3, 2000 | Issued |
| 09/564868 | Semiconductor power module with high speed operation and miniaturization | May 3, 2000 | Abandoned |