Search

Roy Karl Potter

Examiner (ID: 13991, Phone: (571)272-1842 , Office: P/2822 )

Most Active Art Unit
2822
Art Unit(s)
2822, 2508, 2811, 3621
Total Applications
2584
Issued Applications
2409
Pending Applications
46
Abandoned Applications
141

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4410884 [patent_doc_number] => 06271580 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-07 [patent_title] => 'Leads under chip in conventional IC package' [patent_app_type] => 1 [patent_app_number] => 9/301710 [patent_app_country] => US [patent_app_date] => 1999-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4420 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 209 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/271/06271580.pdf [firstpage_image] =>[orig_patent_app_number] => 301710 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/301710
Leads under chip in conventional IC package Apr 28, 1999 Issued
Array ( [id] => 4301733 [patent_doc_number] => 06198167 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-06 [patent_title] => 'Semiconductor structure exhibiting reduced contact resistance and method for fabrication' [patent_app_type] => 1 [patent_app_number] => 9/301567 [patent_app_country] => US [patent_app_date] => 1999-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 3115 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/198/06198167.pdf [firstpage_image] =>[orig_patent_app_number] => 301567 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/301567
Semiconductor structure exhibiting reduced contact resistance and method for fabrication Apr 28, 1999 Issued
Array ( [id] => 4292758 [patent_doc_number] => 06268653 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-31 [patent_title] => 'Semiconductor laser diode multi-chip module' [patent_app_type] => 1 [patent_app_number] => 9/262617 [patent_app_country] => US [patent_app_date] => 1999-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 1199 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/268/06268653.pdf [firstpage_image] =>[orig_patent_app_number] => 262617 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/262617
Semiconductor laser diode multi-chip module Mar 3, 1999 Issued
Array ( [id] => 4253407 [patent_doc_number] => 06137159 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-24 [patent_title] => 'Lead on chip semiconductor device and method of fabricating the same' [patent_app_type] => 1 [patent_app_number] => 9/258300 [patent_app_country] => US [patent_app_date] => 1999-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 23 [patent_no_of_words] => 6969 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/137/06137159.pdf [firstpage_image] =>[orig_patent_app_number] => 258300 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/258300
Lead on chip semiconductor device and method of fabricating the same Feb 25, 1999 Issued
Array ( [id] => 4355636 [patent_doc_number] => 06215179 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-10 [patent_title] => 'Semiconductor device' [patent_app_type] => 1 [patent_app_number] => 9/252817 [patent_app_country] => US [patent_app_date] => 1999-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 58 [patent_no_of_words] => 6495 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/215/06215179.pdf [firstpage_image] =>[orig_patent_app_number] => 252817 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/252817
Semiconductor device Feb 18, 1999 Issued
Array ( [id] => 1522293 [patent_doc_number] => 06414376 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-02 [patent_title] => 'Method and apparatus for reducing isolation stress in integrated circuits' [patent_app_type] => B1 [patent_app_number] => 09/252837 [patent_app_country] => US [patent_app_date] => 1999-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 10 [patent_no_of_words] => 2774 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 13 [patent_words_short_claim] => 27 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/414/06414376.pdf [firstpage_image] =>[orig_patent_app_number] => 09252837 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/252837
Method and apparatus for reducing isolation stress in integrated circuits Feb 18, 1999 Issued
Array ( [id] => 4362861 [patent_doc_number] => 06175153 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-16 [patent_title] => 'Semiconductor device' [patent_app_type] => 1 [patent_app_number] => 9/241402 [patent_app_country] => US [patent_app_date] => 1999-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 23 [patent_no_of_words] => 2422 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 228 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/175/06175153.pdf [firstpage_image] =>[orig_patent_app_number] => 241402 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/241402
Semiconductor device Feb 1, 1999 Issued
Array ( [id] => 1169707 [patent_doc_number] => 06756657 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-06-29 [patent_title] => 'Method of preparing a semiconductor having controlled crystal orientation' [patent_app_type] => B1 [patent_app_number] => 09/238579 [patent_app_country] => US [patent_app_date] => 1999-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 40 [patent_no_of_words] => 16547 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 31 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/756/06756657.pdf [firstpage_image] =>[orig_patent_app_number] => 09238579 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/238579
Method of preparing a semiconductor having controlled crystal orientation Jan 27, 1999 Issued
Array ( [id] => 4275299 [patent_doc_number] => 06307254 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-23 [patent_title] => 'Technique for attaching die to leads' [patent_app_type] => 1 [patent_app_number] => 9/233339 [patent_app_country] => US [patent_app_date] => 1999-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 4507 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/307/06307254.pdf [firstpage_image] =>[orig_patent_app_number] => 233339 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/233339
Technique for attaching die to leads Jan 18, 1999 Issued
Array ( [id] => 1553123 [patent_doc_number] => 06400032 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-04 [patent_title] => 'Method and apparatus for packaging flip chip bare die on printed circuit boards' [patent_app_type] => B1 [patent_app_number] => 09/233358 [patent_app_country] => US [patent_app_date] => 1999-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 3113 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/400/06400032.pdf [firstpage_image] =>[orig_patent_app_number] => 09233358 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/233358
Method and apparatus for packaging flip chip bare die on printed circuit boards Jan 18, 1999 Issued
Array ( [id] => 4310604 [patent_doc_number] => 06252309 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-26 [patent_title] => 'Packaged semiconductor substrate' [patent_app_type] => 1 [patent_app_number] => 9/227580 [patent_app_country] => US [patent_app_date] => 1999-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 1536 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/252/06252309.pdf [firstpage_image] =>[orig_patent_app_number] => 227580 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/227580
Packaged semiconductor substrate Jan 7, 1999 Issued
Array ( [id] => 4302276 [patent_doc_number] => 06187615 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-13 [patent_title] => 'Chip scale packages and methods for manufacturing the chip scale packages at wafer level' [patent_app_type] => 1 [patent_app_number] => 9/222250 [patent_app_country] => US [patent_app_date] => 1998-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 25 [patent_no_of_words] => 3430 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/187/06187615.pdf [firstpage_image] =>[orig_patent_app_number] => 222250 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/222250
Chip scale packages and methods for manufacturing the chip scale packages at wafer level Dec 27, 1998 Issued
Array ( [id] => 4413902 [patent_doc_number] => 06310392 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-30 [patent_title] => 'Stacked micro ball grid array packages' [patent_app_type] => 1 [patent_app_number] => 9/221350 [patent_app_country] => US [patent_app_date] => 1998-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 20 [patent_no_of_words] => 5817 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/310/06310392.pdf [firstpage_image] =>[orig_patent_app_number] => 221350 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/221350
Stacked micro ball grid array packages Dec 27, 1998 Issued
Array ( [id] => 1478835 [patent_doc_number] => 06344667 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-02-05 [patent_title] => 'Wiring board with reduced radiation of undesired electromagnetic waves' [patent_app_type] => B1 [patent_app_number] => 09/221120 [patent_app_country] => US [patent_app_date] => 1998-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 30 [patent_no_of_words] => 8832 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/344/06344667.pdf [firstpage_image] =>[orig_patent_app_number] => 09221120 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/221120
Wiring board with reduced radiation of undesired electromagnetic waves Dec 27, 1998 Issued
Array ( [id] => 4310187 [patent_doc_number] => 06326682 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-12-04 [patent_title] => 'Hermetically sealed transducer and methods for producing the same' [patent_app_type] => 1 [patent_app_number] => 9/217877 [patent_app_country] => US [patent_app_date] => 1998-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 4437 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/326/06326682.pdf [firstpage_image] =>[orig_patent_app_number] => 217877 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/217877
Hermetically sealed transducer and methods for producing the same Dec 20, 1998 Issued
Array ( [id] => 1391801 [patent_doc_number] => 06552425 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-04-22 [patent_title] => 'Integrated circuit package' [patent_app_type] => B1 [patent_app_number] => 09/216140 [patent_app_country] => US [patent_app_date] => 1998-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 18 [patent_no_of_words] => 4694 [patent_no_of_claims] => 46 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 31 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/552/06552425.pdf [firstpage_image] =>[orig_patent_app_number] => 09216140 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/216140
Integrated circuit package Dec 17, 1998 Issued
Array ( [id] => 1404205 [patent_doc_number] => 06541858 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-04-01 [patent_title] => 'Interconnect alloys and methods and apparatus using same' [patent_app_type] => B1 [patent_app_number] => 09/213697 [patent_app_country] => US [patent_app_date] => 1998-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 12 [patent_no_of_words] => 5715 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 14 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/541/06541858.pdf [firstpage_image] =>[orig_patent_app_number] => 09213697 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/213697
Interconnect alloys and methods and apparatus using same Dec 16, 1998 Issued
Array ( [id] => 4337072 [patent_doc_number] => 06313527 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-06 [patent_title] => 'Dual-dies packaging structure and packaging method' [patent_app_type] => 1 [patent_app_number] => 9/210270 [patent_app_country] => US [patent_app_date] => 1998-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 2594 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 206 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/313/06313527.pdf [firstpage_image] =>[orig_patent_app_number] => 210270 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/210270
Dual-dies packaging structure and packaging method Dec 9, 1998 Issued
Array ( [id] => 4414536 [patent_doc_number] => 06229210 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-08 [patent_title] => 'Device and method for attaching and soldering pre-formed solder spheres to the ball grid array (BGA) integrated circuit package attachment sites in high volume' [patent_app_type] => 1 [patent_app_number] => 9/206197 [patent_app_country] => US [patent_app_date] => 1998-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 3164 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/229/06229210.pdf [firstpage_image] =>[orig_patent_app_number] => 206197 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/206197
Device and method for attaching and soldering pre-formed solder spheres to the ball grid array (BGA) integrated circuit package attachment sites in high volume Dec 3, 1998 Issued
Array ( [id] => 4189592 [patent_doc_number] => 06150709 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-21 [patent_title] => 'Grid array type lead frame having lead ends in different planes' [patent_app_type] => 1 [patent_app_number] => 9/203720 [patent_app_country] => US [patent_app_date] => 1998-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 35 [patent_no_of_words] => 13269 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/150/06150709.pdf [firstpage_image] =>[orig_patent_app_number] => 203720 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/203720
Grid array type lead frame having lead ends in different planes Nov 30, 1998 Issued
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