Roy Karl Potter

Array ( [id] => 4140157 [patent_doc_number] => 06121688 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-19 [patent_title] => 'Anisotropic conductive sheet and printed circuit board' [patent_app_type] => 1 [patent_app_number] => 9/168148 [patent_app_country] => US [patent_app_date] => 1998-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 18 [patent_no_of_words] => 6332 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/121/06121688.pdf [firstpage_image] =>[orig_patent_app_number] => 168148 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1590905 [patent_doc_number] => 06483183 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-11-19 [patent_title] => 'Integrated circuit (IC) package with a microcontroller having an n-bit bus and up to n-pins coupled to the microcontroller' [patent_app_type] => B1 [patent_app_number] => 09/522026 [patent_app_country] => US [patent_app_date] => 1998-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 1745 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 30 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/483/06483183.pdf [firstpage_image] =>[orig_patent_app_number] => 09522026 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4076155 [patent_doc_number] => 06069403 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-30 [patent_title] => 'Power module with lowered inductance and reduced voltage overshoots' [patent_app_type] => 1 [patent_app_number] => 9/167203 [patent_app_country] => US [patent_app_date] => 1998-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 3435 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/069/06069403.pdf [firstpage_image] =>[orig_patent_app_number] => 167203 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4191022 [patent_doc_number] => 06130112 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-10 [patent_title] => 'Semiconductor device' [patent_app_type] => 1 [patent_app_number] => 9/166857 [patent_app_country] => US [patent_app_date] => 1998-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 4596 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/130/06130112.pdf [firstpage_image] =>[orig_patent_app_number] => 166857 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1509544 [patent_doc_number] => 06441495 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-27 [patent_title] => 'Semiconductor device of stacked chips' [patent_app_type] => B1 [patent_app_number] => 09/166260 [patent_app_country] => US [patent_app_date] => 1998-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 30 [patent_no_of_words] => 10478 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/441/06441495.pdf [firstpage_image] =>[orig_patent_app_number] => 09166260 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4278231 [patent_doc_number] => 06323548 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-27 [patent_title] => 'Semiconductor integrated circuit device' [patent_app_type] => 1 [patent_app_number] => 9/161997 [patent_app_country] => US [patent_app_date] => 1998-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 2363 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/323/06323548.pdf [firstpage_image] =>[orig_patent_app_number] => 161997 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4318043 [patent_doc_number] => 06316821 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-13 [patent_title] => 'High density lead frames and methods for plastic injection molding' [patent_app_type] => 1 [patent_app_number] => 9/162107 [patent_app_country] => US [patent_app_date] => 1998-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3638 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/316/06316821.pdf [firstpage_image] =>[orig_patent_app_number] => 162107 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1440956 [patent_doc_number] => 06335222 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-01-01 [patent_title] => 'Microelectronic packages with solder interconnections' [patent_app_type] => B1 [patent_app_number] => 09/157047 [patent_app_country] => US [patent_app_date] => 1998-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 14 [patent_no_of_words] => 7445 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 17 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/335/06335222.pdf [firstpage_image] =>[orig_patent_app_number] => 09157047 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4180085 [patent_doc_number] => 06084295 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-04 [patent_title] => 'Semiconductor device and circuit board used therein' [patent_app_type] => 1 [patent_app_number] => 9/148330 [patent_app_country] => US [patent_app_date] => 1998-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 12 [patent_no_of_words] => 4077 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/084/06084295.pdf [firstpage_image] =>[orig_patent_app_number] => 148330 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4297847 [patent_doc_number] => 06236116 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-22 [patent_title] => 'Semiconductor device having a built-in heat sink and process of manufacturing same' [patent_app_type] => 1 [patent_app_number] => 9/146417 [patent_app_country] => US [patent_app_date] => 1998-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 2988 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/236/06236116.pdf [firstpage_image] =>[orig_patent_app_number] => 146417 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1461530 [patent_doc_number] => 06392296 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-21 [patent_title] => 'Silicon interposer with optical connections' [patent_app_type] => B1 [patent_app_number] => 09/143880 [patent_app_country] => US [patent_app_date] => 1998-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 19 [patent_no_of_words] => 7551 [patent_no_of_claims] => 52 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/392/06392296.pdf [firstpage_image] =>[orig_patent_app_number] => 09143880 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4337006 [patent_doc_number] => 06313522 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-06 [patent_title] => 'Semiconductor structure having stacked semiconductor devices' [patent_app_type] => 1 [patent_app_number] => 9/141690 [patent_app_country] => US [patent_app_date] => 1998-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7651 [patent_no_of_claims] => 43 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/313/06313522.pdf [firstpage_image] =>[orig_patent_app_number] => 141690 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4413932 [patent_doc_number] => 06310394 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-30 [patent_title] => 'Reduced parasitic capacitance semiconductor devices' [patent_app_type] => 1 [patent_app_number] => 9/139685 [patent_app_country] => US [patent_app_date] => 1998-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 2841 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/310/06310394.pdf [firstpage_image] =>[orig_patent_app_number] => 139685 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1505497 [patent_doc_number] => 06465880 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-15 [patent_title] => 'IC card indicating state of usage and system therefor' [patent_app_type] => B1 [patent_app_number] => 09/138637 [patent_app_country] => US [patent_app_date] => 1998-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 23 [patent_no_of_words] => 8825 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 22 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/465/06465880.pdf [firstpage_image] =>[orig_patent_app_number] => 09138637 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4366338 [patent_doc_number] => 06255707 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-03 [patent_title] => 'Semiconductor laser reliability test structure and method' [patent_app_type] => 1 [patent_app_number] => 9/138527 [patent_app_country] => US [patent_app_date] => 1998-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 4317 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/255/06255707.pdf [firstpage_image] =>[orig_patent_app_number] => 138527 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1596988 [patent_doc_number] => 06384425 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-07 [patent_title] => 'Nonconductive substrate forming a strip or a panel on which a multiplicity of carrier elements is formed' [patent_app_type] => B1 [patent_app_number] => 09/137924 [patent_app_country] => US [patent_app_date] => 1998-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2685 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/384/06384425.pdf [firstpage_image] =>[orig_patent_app_number] => 09137924 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4414412 [patent_doc_number] => 06229201 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-08 [patent_title] => 'Integrated circuit having a parasitic resonance filter' [patent_app_type] => 1 [patent_app_number] => 9/136857 [patent_app_country] => US [patent_app_date] => 1998-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 12 [patent_no_of_words] => 3992 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/229/06229201.pdf [firstpage_image] =>[orig_patent_app_number] => 136857 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4187376 [patent_doc_number] => 06020634 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-01 [patent_title] => 'Replaceable power module' [patent_app_type] => 1 [patent_app_number] => 9/135197 [patent_app_country] => US [patent_app_date] => 1998-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2269 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/020/06020634.pdf [firstpage_image] =>[orig_patent_app_number] => 135197 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4204467 [patent_doc_number] => 06077726 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-20 [patent_title] => 'Method and apparatus for stress relief in solder bump formation on a semiconductor device' [patent_app_type] => 1 [patent_app_number] => 9/124720 [patent_app_country] => US [patent_app_date] => 1998-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2093 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/077/06077726.pdf [firstpage_image] =>[orig_patent_app_number] => 124720 [rel_patent_id] =>[rel_patent_doc_number] =>)